Datasheet

Chapter 14. UART Modules 14-29
Operation
• Interrupt handling—Consists of SIRQ (sheet 4), which is executed after the UART
module generates an interrupt caused by a change-in-break (beginning of a break).
SIRQ then clears the interrupt source, waits for the next change-in-break interrupt
(end of break), clears the interrupt source again, then returns from exception
processing to the system monitor.
14.5.6.1 UART Module Initialization Sequence
NOTE:
UART module registers can be accessed by word or byte
operations, but only data byte D[7:0] is valid.
Table 14-14 shows the UART module initialization sequence.
Table 14-14. UART Module Initialization Sequence
Register Setting
UCRn Reset the receiver and transmitter.
Reset the mode pointer (MISC[2–0] = 0b001).
UIVRn Program the vector number for a UART module interrupt.
UIMRn Enable the preferred interrupt sources.
UACRn Initialize the input enable control (IEC bit).
UCSRn Select the receiver and transmitter clock. Use timer as source if required.
UMR1n If preferred, program operation of receiver ready-to-send (RxRTS bit).
Select receiver-ready or FIFO-full notification (RxRDY/FFULL bit).
Select character or block error mode (ERR bit).
Select parity mode and type (PM and PT bits).
Select number of bits per character (B/Cx bits).
UMR2n Select the mode of operation (CMx bits).
If preferred, program operation of transmitter ready-to-send (TxRTS).
If preferred, program operation of clear-to-send (TxCTS bit).
Select stop-bit length (SBx bits).
UCR
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