Datasheet

Chapter 17. Signal Descriptions 17-13
Clock and Reset Signals
17.4.3 Bus Driven (BD)
The MCF5307 asserts BD to indicate that it is the current master and is driving the bus. The
MCF5307 behaves as follows:
• If the MCF5307 is the bus master but is not using the bus, BD
is asserted.
• If the MCF5307 loses mastership during a transfer, it completes the last transfer of
the access, negates BD
, and three-states all bus signals on the rising edge of
BCLKO.
• If the MCF5307 loses bus mastership during an idle clock cycle, it three-states all
bus signals on the rising edge of BCLKO.
•BD
cannot be negated unless BG is negated.
17.5 Clock and Reset Signals
The clock and reset signals configure the MCF5307 and provide interface signals to the
external system.
17.5.1 Reset In (RSTI)
Asserting RSTI causes the MCF5307 to enter reset exception processing. When RSTI is
recognized, BR
and BD are negated and the address bus, data bus, TT, SIZ, R/W, AS, and
TS
are three-stated. RSTO is asserted automatically when RSTI is asserted.
17.5.2 Clock Input (CLKIN)
CLKIN is the MCF5307 input clock frequency to the on-board phase-locked-loop (PLL)
clock generator. CLKIN is used to internally clock or sequence the MCF5307 internal bus
interface at a selected multiple of the input frequency used for internal module logic.
17.5.3 Bus Clock Output (BCLKO)
The internal PLL generates BCLKO and can be programmed to be 1/2, 1/3, or 1/4 of the
processor clock frequency. BCLKO should be used as the bus timing reference.
17.5.4 Reset Out (RSTO)
After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is
asserted. When the PLL regains its lock, RST
O negates again. This signal can be used to
reset external devices.
17.5.5 Data/Configuration Pins (D[7:0])
This section describes data pins, D[7:0], that are read at reset for configuration. Table 17-11
shows pin assignments.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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