Datasheet

17-16 MCF5307 User’s Manual
DRAM Controller Signals
17.6.1 Chip-Select (CS[7:0])
Each chip select can be programmed for a base address location and for masking addresses,
port size and burst-capability indication, wait-state generation, and internal/external
termination.
Reset clears all chip select programming; CS
0 is the only chip select initialized out of reset.
CS
0 is also unique because it can function at reset as a global chip select that allows boot
ROM to be selected at any defined address space. Port size and termination (internal vs.
external) for boot CS
0 are configured by the levels on D[7:5] on the rising edge of RSTI,
as described in Section 17.5.5.1, “D[7:5Boot Chip-Select (CS0) Configuration.”
The chip-select implementation is described in Chapter 10, “Chip-Select Module.”
17.6.2 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0])
The four byte enables are multiplexed with the MCF5307 byte-write-enable signals. Each
pin can be individually programmed through the chip-select control registers (CSCRs). For
each chip select, assertion of byte enables for reads and byte-write enables for write cycles
can be programmed. Alternatively, users can program byte-write enables to assert on writes
and no byte enable assertion for read transfers.
17.6.3 Output Enable (OE)
The output enable (OE) signal is sent to the interfacing memory and/or peripheral to enable
a read transfer. OE
is asserted only when a chip select matches the current address decode.
17.7 DRAM Controller Signals
The DRAM signals in the following sections interface to external DRAM. DRAM with
widths of 8, 16, and 32 bits are supported and can access as much as 512 Mbytes of DRAM.
17.7.1 Row Address Strobes (RAS[1:0])
The row address strobes (RAS[1:0]) interface to RAS inputs on industry-standard
ADRAMs. When SDRAMs are used, these signals interface to the chip-select lines of the
SDRAMs within a memory block. Thus, there is one RAS
line for each memory block.
17.7.2 Column Address Strobes (CAS[3:0])
The column address strobes (CAS[3:0]) interface to CAS inputs on industry-standard
DRAMs. These provide CAS
for a given ADRAM block. When SDRAMs are used, CAS
signals control the byte enables for standard SDRAMs (referred to as DQMx). CAS3
accesses the LSB and CAS0 accesses the MSB of data.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...