Datasheet

Chapter 17. Signal Descriptions 17-23
Debug Module/JTAG Signals
17.14.5 Test Clock (TCK)
TCK is the dedicated JTAG test logic clock independent of the MCF5307 processor clock.
Various JTAG operations occur on the rising or falling edge of TCK. Holding TCK high or
low for an indefinite period does not cause JTAG test logic to lose state information. If TCK
is not used, it must be tied to ground.
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