Datasheet

18-6 MCF5307 User’s Manual
Data Transfer Operation
Figure 18-4. Data Transfer State Transition Diagram
Table 18-4 describes the states as they appear in subsequent timing diagrams. Note that the
TT[1:0], TM[2:0], and TIP
functions are chosen in the PAR, as described in Section 15.1.1,
“Pin Assignment Register (PAR).”
Table 18-4. Bus Cycle States
State Cycle BCLKO Description
S0 All High The read or write cycle is initiated. On the rising edge of BCLKO, the MCF5307
places a valid address on the address bus, asserts TIP
, and drives R/W high for
a read and low for a write, if these signals are not already in the appropriate
state. The MCF5307 asserts TT[1:0], TM[2:0], SIZ[1:0], and TS
on the rising
edge of BCLKO.
S1 All Low AS
asserts on the falling edge of BCLKO, indicating that the address and
attributes are stable. The appropriate CS
x, BE/BWE, and OE signals assert on
the BCLKO falling edge.
Fast termination T
A must be asserted during S1. Data is made available by the external device
and is sampled on the rising edge of BCLKO with T
A asserted.
S2 Read/write
(skipped for fast
termination)
High TS
is negated on the rising edge of BCLKO.
Write The data bus is driven out of high impedance as data is placed on the bus on
the rising edge of BCLKO.
S3 Read/write
(skipped for fast
termination)
Low The MCF5307 waits for T
A assertion. If TA is not sampled as asserted before
the rising edge of BCLKO at the end of the first clock cycle, the MCF5307
inserts wait states (full clock cycles) until T
A is sampled as asserted.
Read Data is made available by the external device on the falling edge of BCLKO and
is sampled on the rising edge of BCLKO with T
A asserted.
S4 All High The external device should negate T
A.
Read (including
fast termination)
The external device can stop driving data after the rising edge of BCLKO.
However, data could be driven up to S5.
S0
S3
S5
S4
S1
S2
Basic
Next Cycle
Wait
States
Read/Write
Fast
Termination
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eescale S
emiconduct
or
, I
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