Datasheet

Chapter 18. Bus Operation 18-7
Data Transfer Operation
NOTE:
An external device has at most two BCLKO cycles after the
start of S4 to three-state the data bus after data is sampled in S3.
This applies to basic read cycles, fast-termination cycles, and
the last transfer of a burst.
18.4.3 Read Cycle
During a read cycle, the MCF5307 receives data from memory or from a peripheral device.
Figure 18-5 is a read cycle flowchart.
Figure 18-5. Read Cycle Flowchart
The read cycle timing diagram is shown in Figure 18-6.
NOTE:
In the following timing diagrams, T
A waveforms apply for chip
selects programmed to enable either internal or external
termination. T
A assertion should look the same in either case.
S5 S5 Low AS, CS, BE/BWE, and OE are negated on the BCLKO falling edge. The
MCF5307 stops driving address lines and R/W
on the rising edge of BCLKO,
terminating the read or write cycle. At the same time, the MCF5307 negates
TT[1:0], TM[2:0], TIP
, and SIZ[1:0] on the rising edge of BCLKO.
Note that the rising edge of BCLKO may be the start of S0 for the next access
cycle; in this case, TIP
remains asserted and R/W may not transition,
depending on the nature of the back-to-back cycles.
Read The external device stops driving data between S4 and S5.
Write The data bus returns to high impedance on the rising edge of BCLKO. The
rising edge of BCLKO may be the start of S0 for the next access.
Table 18-4. Bus Cycle States (Continued)
State Cycle BCLKO Description
System
1. Set R/W
to read
2. Place address on A[31:0]
3. Assert TT[1:0], TM[2:0], TIP
,
and SIZ[1:0]
4. Assert TS
5. Assert AS
6. Negate TS
1. Decode address and select the
appropriate slave device.
2. Drive data on D[31:0]
3. Assert TA
1. Sample TA low and latch data
1. Negate TA.
2. Stop driving D[31:0]
1. Start next cycle
MCF5307
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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