Datasheet

Chapter 18. Bus Operation 18-17
Bus Errors
Instruction words and extension words (opcodes) must reside on word boundaries.
Attempting to prefetch a misaligned instruction word causes an address error exception.
The MCF5307 converts misaligned, cache-inhibited operand accesses to multiple aligned
accesses. Figure 18-21 shows the transfer of a longword operand from a byte address to a
32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The
slave device supplies the byte and acknowledges the data transfer. When the MCF5307
starts the second cycle, SIZ[1:0] specify a word transfer with a byte offset of 0x2. The next
two bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte
offset is now 0x0, the port supplies the final byte, and the operation is complete.
Figure 18-21. Example of a Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are
loaded into the cache. The example in Figure 18-22 differs from the one in Figure 18-21 in
that the operand is word-sized and the transfer takes only two bus cycles.
Figure 18-22. Example of a Misaligned Word Transfer (32-Bit Port)
NOTE:
External masters using internal MCF5307 chip selects and
default memory control signals must initiate aligned transfers.
18.6 Bus Errors
The MCF5307 has no bus monitor. If the auto-acknowledge feature is not enabled for the
address that generates the error, the bus cycle can be terminated by asserting T
A or by using
the software watchdog timer. If it is required that the MCF5307 handle a bus error
differently, an interrupt handler can be invoked by asserting an interrupt to the core along
with T
A when the bus error occurs.
18.7 Interrupt Exceptions
A peripheral device uses the interrupt-request signals (IRQx) to signal the core to take an
interrupt exception when it needs the MCF5307 or is ready to send information to it. The
interrupt transfers control to an appropriate routine.
Transfer 1
Transfer 2
Transfer 3
—
—
Byte 3
Byte 0
—
—
—
Byte 1
—
—
Byte 2
—
31 24 23 16 15 8 7 0
001
010
100
A[2:0]
Transfer 1
Transfer 2
—
Byte 0
—
—
—
—
Byte 0
—
31 24 23 16 15 8 7 0
001
100
A[2:0]
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