Datasheet

18-30 MCF5307 User’s Manual
General Operation of External Master Transfers
Figure 18-30. Three-Wire Implicit and Explicit Bus Mastership
In Figure 18-30, the external device is bus master during C1 and C2, releasing control in
C3, at which time the external arbiter asserts BG
to the MCF5307. During C4 and C5, the
MCF5307 is implicit master because no internal access is pending. In C5, an internal bus
request becomes pending, causing the MCF5307 to take explicit bus mastership in C6 by
asserting BR
and BD. In C7, the external device removes the bus grant to the MCF5307.
The MCF5307 does not release the bus (the MCF5307 asserts BD
) until the transfer ends.
NOTE:
The MCF5307 can start a transfer in the cycle after BG
is
asserted. The external arbiter should not assert BG
to the
MCF5307 until the previous external master stops driving the
bus. Asserting BG
during another external master’s transfer
may damage the part.
R/W
TIP
TS
AS
D[31:0]
T
A
BG
BD
External Master
Explicit
Mastership
Implicit
Mastership
C1 C2 C4 C5 C6 C7C3 C8 C9
BR
MCF5307
BCLKO
A[31:0], TT[1:0]
SIZ[1:0], TM[2:0]
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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