Datasheet

Chapter 18. Bus Operation 18-31
General Operation of External Master Transfers
Figure 18-31. Three-Wire Bus Arbitration
In Figure 18-31, the external device is bus master during C1 and C2. During C2, the
MCF5307 requests the external bus because of a pending internal transfer. On C3, the
external releases mastership and the external arbiter grants the bus to the MCF5307 by
asserting BG
. At this point, an internal is access pending so the MCF5307 asserts BD
during C4 and begins the access. Thus, the MCF5307 becomes the explicit bus master. Also
during C4, the external arbiter removes the grant from the MCF5307 by negating BG
.
Because the MCF5307 is bus master, it continues to assert BD
until the current transfer
completes. Because BG
is negated, the MCF5307 negates BD during C9 and three-states
the external bus, thereby passing mastership to an external device.
The MCF5307 can assert BR
to signal the external arbiter that it needs the bus. However,
there is no guarantee that when the bus is granted to the MCF5307 that a bus cycle will be
performed. At best, BR
must be used as a status output that indicates when the MCF5307
needs the bus, but not as an indication that the MCF5307 is in a certain bus arbitration state.
Figure 18-32 is a high-level state diagram for MCF5307 bus arbitration protocol.
Table 18-6 describes the four states shown in Figure 18-32.
R/W
TIP
TS
AS
D[31:0]
T
A
BG
BD
External
Master
C1 C2 C4 C5 C6 C7C3 C8 C9
BR
MCF5307
BCLKO
A[31:0], TT[1:0]
SIZ[1:0], TM[2:0]
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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