Datasheet

Chapter 18. Bus Operation 18-35
Reset Operation
See Section 17.5.5, “Data/Configuration Pins (D[7:0]).” Motorola recommends that the
data pins be driven rather than using a weak pull-up or pull-down resistor. Table 17-1 lists
the encoding of these pins sampled at reset.
18.10.2 Software Watchdog Reset
A software watchdog reset is performed if the executing software does not provide the
correct write data sequence with the enable-control bit set. This reset helps prevent runaway
software or unterminated bus cycles. Figure 18-34 is a functional timing diagram of the
software watchdog reset operation, showing RST
O and bus signal relationships.
Table 18-12. Data Pin Configuration
Pin Function
D7 Auto-Acknowledge Configuration (AA_CONFIG)
D[6:5] Port Size Configuration (PS_CONFIG[1:0])
D4 Address Configuration (ADDR_CONFIG/D4)
D[3:2] Frequency of CLKIN (FREQ[1:0])
D[1:0] Ratio of BCLKO/Processor Clock {DIVIDE[1:0])
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