Datasheet

19-2 MCF5307 User’s Manual
JTAG Signal Descriptions
Figure 19-1 is a block diagram of the MCF5307 implementation of the 1149.1 IEEE
standard. The test logic includes several test data registers, an instruction register,
instruction register control decode, and a 16-state dedicated TAP controller.
Figure 19-1. JTAG Test Logic Block Diagram
19.2 JTAG Signal Descriptions
JTAG operation on the MCF5307 is enabled when MTMOD0 is high (logic 1), as described
in Table 19-1. Otherwise, JTAG TAP signals, TCK, TMS, TDI, TDO, and TRST
, are
interpreted as the debug port pins. MTMOD0 should not be changed while RSTI
is
asserted.
Table 19-1. JTAG Pin Descriptions
Pin Description
TCK Test clock. The dedicated JTAG test logic clock is independent of the MCF5307 processor clock. Various
JTAG operations occur on the rising or falling edge of TCK. Internal JTAG controller logic is designed such
that holding TCK high or low indefinitely does cause the JTAG test logic to lose state information. If TCK is
not used, it should be tied to ground.
TMS/
BKPT
Test mode select (MTMOD0 high)/breakpoint (MTMOD0 low). TMS provides the JTAG controller with
information to determine the test operation mode. The states of TMS and of the internal 16-state JTAG
controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current
state or advances to the next state. This directly controls whether JTAG data or instruction operations
occur. TMS has an internal pull-up, so if it is not driven low, its value defaults to a logic level of 1. If TMS is
not used, it should be tied to VDD. BKPT
signals a hardware breakpoint to the processor in debug mode.
See Chapter 5, “Debug Support.”
Test Data Registers
TDI
TMS
TRST
TDO
V+
V+
V+
Boundary Scan Register
ID Code
Bypass
3-Bit Instruction Register
3-Bit Instruction Decode
M
U
X
TAP
M
U
X
TCK
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