Datasheet

Chapter 19. IEEE 1149.1 Test Access Port (JTAG) 19-7
JTAG Register Descriptions
19.4.3 JTAG Boundary-Scan Register
The MCF5307 model includes an IEEE Standard 1149.1-compliant boundary-scan register
connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions
are selected. This register captures signal data on the input pins, forces fixed values on the
output pins, and selects the direction and drive characteristics (a logic value or high
impedance) of the bidirectional and three-state pins. Table 19-4 shows MCF5307
boundary-scan register bits.
Table 19-4. Boundary-Scan Bit Definitions
Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type
0 O.Ctl PP0 enable — 120 O.Pin BE0
O
1 O.Pin PP0 I/O 121 O.Pin SCKE O
2 I.Pin PP0 I/O 122 O.Pin SCAS
O
3 IO.Ctl PP1 enable — 123 O.Pin SRAS
O
4 O.Pin PP1 I/O 124 O.Pin DRAMW
O
5 I.Pin PP1 I/O 125 O.Pin CAS3
O
6 IO.Ctl PP2 enable — 126 O.Pin CAS2
O
7 O.Pin PP2 I/O 127 O.Pin CAS1
O
8 I.Pin PP2 I/O 128 O.Pin CAS0
O
9 IO.Ctl PP3 enable — 129 O.Pin RAS1
O
10 O.Pin PP3 I/O 130 O.Pin RAS0
O
11 I.Pin PP3 I/O 131 I.Pin TIN1 I
12 IO.Ctl PP4 enable — 132 I.Pin TIN0 I
13 O.Pin PP4 I/O 133 O.Pin TOUT0 O
14 I.Pin PP4 I/O 134 O.Pin TOUT1 O
15 IO.Ctl PP5 enable — 135 I.Pin BG
I
16 O.Pin PP5 I/O 136 O.Pin BD
O
17 I.Pin PP5 I/O 137 O.Pin BR
O
18 IO.Ctl PP6 enable — 138 I.Pin IRQ1
I
19 O.Pin PP6 I/O 139 I.Pin IRQ3
I
20 I.Pin PP6 I/O 140 I.Pin IRQ5
I
21 IO.Ctl PP7 enable — 141 I.Pin IRQ7
I
22 O.Pin PP7 I/O 142 I.Pin RSTI
I
23 I.Pin PP7 I/O 143 O.Pin TS
I/O
24 O.Pin PST3 O 144 I.Pin TS
I/O
25 O.Pin PST2 O 145 IO.Ctl T
A enable —
26 O.Pin PST1 O 146 O.Pin T
A I/O
27 O.Pin PST0 O 147 I.Pin T
A I/O
28 O.Pin DDATA3 O 148 O.Pin R/W
I/O
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eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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