Datasheet

20-2 MCF5307 User’s Manual
Clock Timing Specifications
voltage of Vcc = 3.3 Vdc ± 0.3 Vdc.
20.2 Clock Timing Specifications
Table 20-4 lists specifications for the clock timing parameters shown in Figure 20-1 and
Figure 20-2.
Table 20-3. DC Electrical Specifications
Characteristic Symbol Min Max Units
Operation voltage range V
cc
3.0 3.6 V
Input high voltage V
IH
2.0 3.6 V
Input low voltage V
IL
-0.5 0.8 V
Input signal undershoot ——0.8 V
Input signal overshoot ——0.8 V
Input leakage current @ 0.5/2.4 V during normal operation I
in
— 20 µA
High impedance (three-state) leakage current @ 0.5/2.4 V during
normal operation
I
TSI
— 20 µA
Signal low input current, V
IL
= 0.8 V
1
1
BKPT/TMS, DSI/TDI, DSCLK/TRST
I
IL
01 mA
Signal high input current, V
IH =
2.0 V
1
I
IH
01 mA
Output high voltage I
OH
= 6 mA
2
, 12 mA
3
2
D[31:0], A[23:0], PP[15:0],TS, TA, SIZ[1:0], R/W, BR, BD, RSTO, AS, CS[7:0], BE[3:0], OE, PSTCLK,
PST[3:0], DDATA[3:0], DSO, TOUT[1:0], SCL, SDA, R
TS[1:0], TXD[1:0]
3
BCLKO, RAS[1:0], CAS[3:0], DRAMW, SCKE, SRAS, SCAS
V
OH
2.4 — V
Output low voltage I
OL
= 6 mA
2
, 12 mA
3
V
OL
— 0.5 V
Load capacitance (all outputs) C
L
— 50 pF
Capacitance
4
, V
in
= 0 V, f = 1 MHz
4
Capacitance C
IN
is periodically sampled rather than 100% tested.
C
IN
— 10 pF
Table 20-4. Clock Timing Specification
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
C1 CLKIN cycle time 30 — 22 — nS
C2 CLKIN rise time (0.5V to 2.4 V) — 5 — 5nS
C3 CLKIN fall time (2.4V to 0.5 V) — 5 — 5nS
C4 CLKIN duty cycle (at 1.5 V) 40 60 40 60 %
C5 PSTCLK cycle time 15 — 11 — nS
C6 PSTCLK duty cycle (at 1.5 V) 40 60 40 60 %
C7 BCLKO cycle time 30 — 22 — nS
C8 BCLKO duty cycle (at 1.5 V) 45 55 45 55 %
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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