Datasheet

Chapter 20. Electrical Specifications 20-3
Input/Output AC Timing Specifications
Figure 20-1 shows timings for the parameters listed in Table 20-4.
Figure 20-1. Clock Timing
Figure 20-2 shows PSTCLK timings for parameters listed in Table 20-4.
Figure 20-2. PSTCLK Timing
20.3 Input/Output AC Timing Specifications
Table 20-5 lists specifications for parameters shown in Figure 20-3 and Figure 20-4. Note
that inputs IRQ
[7,5,3,1], BKPT, and AS are synchronized internally; that is, the logic level
is validated if the value does not change for two consecutive rising BCLKO edges. Setup
and hold times must be met only if recognition on a particular clock edge is required.
Table 20-5. Input AC Timing Specification
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
B1
1
Valid to BCLKO rising (setup) 7.5 — 5.5 — nS
B2
1
BCLKO rising to invalid (hold) 3 — 2 — nS
B3
2
Valid to BCLKO falling (setup) 7.5 — 5.5 — nS
B4
2
BCLKO falling to invalid (hold) 3 — 2 — nS
BCLKO
BCLKO
C1
C4 C4
C3
C2
C7
C8 C8
Note: Input and output AC timing specifications are measured to BCLKO with a 50-pF load capacitance
(not including pin capacitance).
PSTCLK
C6 C6
C5
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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