Datasheet

20-6 MCF5307 User’s Manual
Input/Output AC Timing Specifications
Figure 20-4. SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO
Figure 20-5 shows an SDRAM write cycle with EDGESEL tied to buffered BCLKO.
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV NOP PALLNOP
RAS
READ
Row Column
EDGESEL
DRAMW
CAS
B16
B15
B15
B16
B2
B1
B16
B16
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
BCLKO
1
DACR[CASL] = 2
B6
NOP
NOP
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eescale S
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or
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