Datasheet

Chapter 20. Electrical Specifications 20-9
Input/Output AC Timing Specifications
Figure 20-7. SDRAM Write Cycle with EDGESEL Tied High
Figure 20-8 shows an SDRAM read cycle with EDGESEL tied low.
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV PALLNOP
RAS
WRITE
Row Column
BCLKO
DRAMW
CAS
B10
B10
B11a
B11
B11a
0
1 2 3 4 5 6 7 8 9 10 11 12
B10
NOP
1
DACR[CASL] = 2
B11a
B11
B11a
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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