Datasheet

20-10 MCF5307 User’s Manual
Input/Output AC Timing Specifications
Figure 20-8. SDRAM Read Cycle with EDGESEL Tied Low
Figure 20-9 shows an SDRAM write cycle with EDGESEL tied low.
A[31:0]
TS
SRAS
D[31:0]
ACTV NOP PALLNOP
RAS
READ
Row Column
BCLKO
0
DRAMW
CAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
B14
B13
B13
B14
B2
B1
B14
B14
SCAS
1
1
DACR[CASL] = 2
NOP
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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