Datasheet

Chapter 20. Electrical Specifications 20-11
Input/Output AC Timing Specifications
Figure 20-9. SDRAM Write Cycle with EDGESEL Tied Low
Figure 20-10 shows AC timing showing high impedance.
Figure 20-10. AC Output Timing—High Impedance
A[31:0]
TS
SRAS
SCAS
1
D[31:0]
ACTV PALLNOP
RAS
WRITE
Row Column
BCLKO
DRAMW
CAS
B14
B13
B13
B14
B14
B14
0
1 2 3 4 5 6 7 8 9 10 11 12
B13
1
DACR[CASL] = 2
NOP
H1 H2
HIZ
OUTPUTS
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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