Datasheet

Chapter 1. Overview 1-5
MCF5307 Features
• DMA controller
— Four fully programmable channels: two support external requests
— Dual-address and single-address transfer support with 8-, 16-, and 32-bit data
capability
— Source/destination address pointers that can increment or remain constant
— 24-bit transfer counter per channel
— Operand packing and unpacking supported
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Two-bus-clock internal access
— Automatic DMA transfers from on-chip UARTs using internal interrupts
• DRAM controller
— Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, and fast
page mode support
— Up to 512 Mbytes of DRAM
— Programmable timer provides CAS-before-RAS refresh for asynchronous
DRAMs
— Support for two separate memory blocks
•Two UARTs
— Full-duplex operation
— Programmable clock
— Modem control signals available (CTS
, RTS)
— Processor-interrupt capability
• Dual 16-bit general-purpose multiple-mode timers
— 8-bit prescaler
— Timer input and output pins
— Processor-interrupt capability
— Up to 22-nS resolution at 45 MHz
•I
2
C module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and
keypads
— Fully compatible with industry-standard I
2
C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
• System interface module (SIM)
— Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM,
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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