Datasheet

Chapter 20. Electrical Specifications 20-15
I
2
C Input/Output Timing Specifications
20.7 I
2
C Input/Output Timing Specifications
Table 20-10 lists specifications for the I
2
C input timing parameters shown in Figure 20.8.
Table 20-11 lists specifications for the I
2
C output timing parameters shown in Figure 20.8.
Table 20-10. I
2
C Input Timing Specifications between SCL and SDA
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
I1 Start condition hold time 2 — 2 — Bus clocks
I2 Clock low period 8 — 8 — Bus clocks
I3 SCL/SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) — 1 — 1mS
I4 Data hold time 0 — 0 — nS
I5 SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 1 — 1mS
I6 Clock high time 4 — 4 — Bus clocks
I7 Data setup time 0 — 0 — nS
I8 Start condition setup time (for repeated start condition only) 2 — 2 — Bus clocks
I9 Stop condition setup time 2 — 2 — Bus clocks
Table 20-11. I
2
C Output Timing Specifications between SCL and SDA
Num Characteristic
66 MHz 90 MHz
Units
Min Max Min Max
I1
1
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 20-11. The I
2
C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers given
in Table 20-11 are minimum values.
Start condition hold time 6 — 6 — Bus clocks
I2
1
Clock low period 10 — 10 — Bus clocks
I3
2
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time
SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values.
SCL/SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) ———— µS
I4
1
Data hold time 7 — 7 — Bus clocks
I5
3
3
Specified at a nominal 50-pF load.
SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 3 — 3nS
I6
1
Clock high time 10 — 10 — Bus clocks
I7
1
Data setup time 2 — 2 — Bus clocks
I8
1
Start condition setup time (for repeated start
condition only)
20 — 20 — Bus clocks
I9
1
Stop condition setup time 10 — 10 — Bus clocks
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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