Datasheet

1-6 MCF5307 User’s Manual
MCF5307 Features
FLASH, and memory-mapped I/O devices
— Eight fully programmable chip selects, each with a base address register
— Programmable wait states and port sizes per chip select
— User-programmable processor clock/input clock frequency ratio
— Programmable interrupt controller
— Low interrupt latency
— Four external interrupt request inputs
— Programmable autovector generator
— Software watchdog timer
• 16-bit general-purpose I/O interface
• IEEE 1149.1 test (JTAG) module
• System debug support
— Real-time trace for determining dynamic execution path while in emulator mode
— Background debug mode (BDM) for debug features while halted
— Real-time debug support, including 6 user-visible hardware breakpoint registers
supporting a variety of breakpoint configurations
— Supports comprehensive emulator functions through trace and breakpoint logic
• On-chip PLL
— Supports processor clock/bus clock ratios of 66/33, 66/22, 66/16.5, 90/45, 90/30,
and 90/22.5
— Supports low-power mode
• Product offerings
— 75 Dhrystone 2.1 MIPS at 90 MHz
— Implemented in 0.35 µ, triple-layer-metal process technology with 3.3-V
operation (5.0-V compliant I/O pads)
— 208-pin plastic QFP package
— 0°–70° C operating temperature
1.2.1 Process
The MCF5307 is manufactured in a 0.35-µ CMOS process with triple-layer-metal routing
technology. This process combines the high performance and low power needed for
embedded system applications. Inputs are 3.3-V tolerant; outputs are CMOS or open-drain
CMOS with outputs operating from VDD + 0.5 V to GND - 0.5 V, with guaranteed
TTL-level specifications.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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