Datasheet

Appendix A. List of Memory Maps A-7
0x220–
0x22C
Do not access
2
—
0x230 UART interrupt vector
register—(UIVRn)
[p. 14-15]
—
0x234 (Read) UART input
port registers—(UIPn)
[p. 14-15]
—
(Write) Do not access
2
—
0x238 (Read) Do not access
2
—
(Write) UART output
port bit set command
registers—(UOP1n
3
)
[p. 14-15]
—
0x23C (Read) Do not access
2
—
(Write) UART output
port bit reset
command
registers—(UOP0n
3
)
[p. 14-15]
—
1
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a
software reset command. That is, if channel operation is not disabled, undesirable results may occur.
2
This address is for factory testing. Reading this location results in undesired effects and possible
incorrect transmission or reception of characters. Register contents may also be changed.
3
Address-triggered commands
Table A-8. Parallel Port Memory Map
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x244 Parallel port data direction register (PADDR)
[p. 15-2]
Reserved
0x248 Parallel port data register (PADAT) [p. 15-2] Reserved
Table A-9. I
2
C Interface Memory Map
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x280 I
2
C address register
(IADR) [p. 8-6]
Reserved
0x284 I
2
C frequency divider
register (IFDR) [p. 8-7]
Reserved
Table A-7. UART1 Module Programming Model (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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