Datasheet

Appendix A. List of Memory Maps A-9
0x394 DMA interrupt vector
register 2 (DIVR2)
[p. 12-11]
Reserved
0x3C0 Source address register 3 (SAR3) [p. 12-6]
0x3C4 Destination address register 3 (DAR3) [p. 12-7]
0x3C8 DMA control register 3 (DCR3) [p. 12-8]
0x3CC Byte count register 3 (BCR24BIT = 0)
1
Reserved
0x3CC Reserved Byte count register 3 (BCR24BIT = 1)
1
(BCR3) [p. 12-7]
0x3D0 DMA status register 3
(DSR3) [p. 12-10]
Reserved
0x3D4 DMA interrupt vector
register 3 (DIVR3)
[p. 12-11]
Reserved
1
On the 0H55J and 1H55J revisions of the MCF5307, the byte count register of the DMA channels can
accommodate only 16 bits. However, on the newest revision of the MCF5307, an expanded 24-bit byte count
range provides greater flexibility. For this reason, the position of the byte count register (BCR) in the memory
map depends on whether a 16- or 24-bit byte counter is chosen. The selection is made by programming
MPARK[BCR24BIT] in the SIM module.
In the new MCF5307, the 24-bit byte count can be selected by setting BCR24BIT = 1, making DCR[AT]
available. The AT bit selects whether the DMA channels assert an acknowledge during the entire transfer or
only at the final transfer of a DMA transaction.
New applications should take advantage of the full range of the 24-bit byte counter, including the AT bit. The
16-bit byte count option (BCR24BIT = 0) is kept to retain compatibility with older revisions of the MCF5307.
Table A-10. DMA Controller Registers (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
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