Datasheet

1-14 MCF5307 User’s Manual
Programming Model, Addressing Modes, and Instruction Set
1.4.2 User Registers
The user programming model is shown in Figure 1-4 and summarized in Table 1-1.
1.4.3 Supervisor Registers
Table 1-2 summarizes the MCF5307 supervisor-level registers.
Table 1-1. User-Level Registers
Register Description
Data registers
(D0–D7)
These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as
index registers.
Address registers
(A0–A7)
These 32-bit registers serve as software stack pointers, index registers, or base address
registers. The base address registers can be used for word and longword operations. A7
functions as a hardware stack pointer during stacking for subroutine calls and exception handling.
Program counter
(PC)
Contains the address of the instruction currently being executed by the MCF5307 processor
Condition code
register (CCR)
The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous
operation and are used for conditional instruction execution.
MAC status
register (MACSR)
Defines the operating configuration of the MAC unit and contains indicator flags from the results
of MAC instructions.
Accumulator
(ACC)
General-purpose register used to accumulate the results of MAC operations
Mask register
(MASK)
General-purpose register provides an optional address mask for MAC instructions that fetch
operands from memory. It is useful in the implementation of circular queues in operand memory.
Table 1-2. Supervisor-Level Registers
Register Description
Status register (SR) The upper byte of the SR provides interrupt information in addition to a variety of mode indicators
signaling the operating state of the ColdFire processor. The lower byte of the SR is the CCR, as
shown in Figure 1-4.
Vector base register
(VBR)
Defines the upper 12 bits of the base address of the exception vector table used during exception
processing. The low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1
Mbyte address.
Cache configuration
register (CACR)
Defines the operating modes of the Version 4 cache memories. Control fields configuring the
instruction, data, and branch cache are provided by this register, along with the default attributes
for the 4-Gbyte address space.
Access control
registers (ACR0/1)
Define address ranges and attributes associated with various memory regions within the 4-Gbyte
address space. Each ACR defines the location of a given memory region and assigns attributes
such as write-protection and cache mode (copyback, write-through, cacheability). Additionally,
CACR fields assign default attributes to the instruction and data memory spaces.
RAM base address
register (RAMBAR)
Provide the logical base address for the 4-Kbyte SRAM module and define attributes and access
types allowed for the SRAM.
Module base address
register (MBAR)
Defines the logical base address for the memory-mapped space containing the control registers
for the on-chip peripherals.
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eescale S
emiconduct
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Freescale Semiconductor, Inc.
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