Datasheet

Part I. MCF5307 Processor Core I-xvii

Part I

MCF5307 Processor Core

Intended Audience

Part I is intended for system designers who need a general understanding of the

functionality supported by the MCF5307. It also describes the operation of the MCF5307

Contents

• Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the

MCF5307. The chapter begins with a description of enhancements from the V2

ColdFire core, and then fully describes the V3 programming model as it is

implemented on the MCF5307. It also includes a full description of exception

handling, data formats, an instruction set summary, and a table of instruction

timings.

• Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the MCF5307

multiply/accumulate unit, which executes integer multiply, multiply-accumulate,

and miscellaneous register instructions. The MAC is integrated into the operand

execution pipeline (OEP).

• Chapter 4, “Local Memory.” This chapter describes the MCF5307 implementation

of the ColdFire V3 local memory speciﬁcation. It consists of the two following

major sections.

— Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM

(SRAM) implementation. It covers general operations, conﬁguration, and

initialization. It also provides information and examples showing how to

minimize power consumption when using the SRAM.

— Section 4.7, “Cache Overview,” describes the MCF5307 cache implementation,

including organization, conﬁguration, and coherency. It describes cache

operations and how the cache interacts with other memory structures.

• Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug

support in the MCF5307. This revision of the ColdFire debug architecture

encompasses earlier revisions.

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Freescale Semiconductor, Inc.

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