Datasheet

Chapter 2. ColdFire Core 2-21
Chapter 2
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF5307. The
chapter begins with a description of enhancements from the Version 2 (V2) ColdFire core,
and then fully describes the V3 programming model as it is implemented on the MCF5307.
It also includes a full description of exception handling, data formats, an instruction set
summary, and a table of instruction timings.
2.1 Features and Enhancements
The MCF5307 is the first standard product to contain a Version 3 ColdFire microprocessor
core. To reach higher levels of frequency and performance, numerous enhancements were
made to the V2 architecture. Most notable are a deeper instruction pipeline, branch
acceleration, and a unified cache, which together provide 75 (Dhrystone 2.1) MIPS at 90
MHz.
The MCF5307 core design emphasizes performance, and backward compatibility
represents the next step on the ColdFire performance roadmap.
The following list summarizes MCF5307 features:
• Variable-length RISC, clock-multiplied Version 3 microprocessor core
• Two independent, decoupled pipelines—four-stage instruction fetch pipeline (IFP)
and two-stage operand execution pipeline (OEP)
• Eight-instruction FIFO buffer provides decoupling between the pipelines
• Branch prediction mechanisms for accelerating program execution
• 32-bit internal address bus supporting 4 Gbytes of linear address space
• 32-bit data bus
• 16 user-accessible, 32-bit-wide, general-purpose registers
• Supervisor/user modes for system protection
• Vector base register to relocate exception-vector table
• Optimized for high-level language constructs
Fr
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Freescale Semiconductor, Inc.
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