Datasheet
2-40 MCF5307 User’s Manual
Instruction Timing
Table 2-8 describes supervisor-mode instructions.
2.7 Instruction Timing
The timing data presented in this section assumes the following:
• The OEP is loaded with the opword and all required extension words at the
beginning of each instruction execution. This implies that the OEP spends no time
waiting for the IFP to supply opwords and/or extension words.
• The OEP experiences no sequence-related pipeline stalls. For the MCF5307, the
most common example of this type of stall involves consecutive store operations,
excluding the MOVEM instruction. For all store operations (except MOVEM),
TST <ea>y .B,.W,.L Set condition codes
UNLK Ax Unsized Ax →SP; (SP) → Ax; SP + 4 → SP
WDDATA <ea>y .B,.W,.L <ea>y →DDATA port
1
By default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode
execution by setting CSR[UHE].
Table 2-8. Supervisor-Mode Instruction Set Summary
Instruction Operand Syntax Operand Size Operation
CPUSHL (An) Unsized Invalidate instruction cache line
Push and invalidate data cache line
Push data cache line and invalidate (I,D)-cache lines
HALT
1
1
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
none Unsized Enter halted state
MOVE from SR SR, Dx .W SR → Dx
MOVE to SR Dy,SR
#<data>,SR
.W Source → SR
MOVEC Ry,Rc .L Ry → Rc
Rc Register Definition
0x002 Cache control register (CACR)
0x004 Access control register 0 (ACR0)
0x005 Access control register 1 (ACR1)
0x006 Access control register 2 (ACR2)
0x007 Access control register 3 (ACR3)
0x801 Vector base register (VBR)
0xC04 RAM base address register 0 (RAMBAR0)
0xC05 RAM base address register 1 (RAMBAR1)
RTE None Unsized (SP+2) → SR; SP+4 → SP; (SP) → PC; SP + formatfield SP
STOP #<data> .W Immediate data → SR; enter stopped state
WDEBUG <ea-2>y .L <ea-2>y → debug module
Table 2-7. User-Mode Instruction Set Summary (Continued)
Instruction Operand Syntax Operand Size Operation
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