Datasheet

CONTENTS
Paragraph
Number
Title
Page
Number
Contents ix
5.5.3.3.4 Write Memory Location ( WRITE ) ......................................................... 5-27
5.5.3.3.5 Dump Memory Block (
DUMP ).............................................................. 5-29
5.5.3.3.6 Fill Memory Block (
FILL )..................................................................... 5-31
5.5.3.3.7 Resume Execution (
GO )........................................................................ 5-33
5.5.3.3.8 No Operation (
NOP ) .............................................................................. 5-34
5.5.3.3.9 Synchronize PC to the PST/DDATA Lines (
SYNC _ PC ) ....................... 5-35
5.5.3.3.10 Read Control Register (
RCREG ) ............................................................ 5-36
5.5.3.3.11 Write Control Register (
WCREG ) .......................................................... 5-37
5.5.3.3.12 Read Debug Module Register (
RDMREG ) ............................................. 5-38
5.5.3.3.13 Write Debug Module Register (
WDMREG ) ........................................... 5-39
5.6 Real-Time Debug Support................................................................................ 5-39
5.6.1 Theory of Operation...................................................................................... 5-40
5.6.1.1 Emulator Mode ......................................................................................... 5-41
5.6.2 Concurrent BDM and Processor Operation.................................................. 5-41
5.7 Motorola-Recommended BDM Pinout............................................................. 5-42
5.8 Processor Status, DDATA Definition............................................................... 5-42
5.8.1 User Instruction Set ...................................................................................... 5-43
5.8.2 Supervisor Instruction Set............................................................................. 5-46
Part II
System Integration Module (SIM)
Chapter 6
SIM Overview
6.1 Features............................................................................................................... 6-1
6.2 Programming Model........................................................................................... 6-3
6.2.1 SIM Register Memory Map............................................................................ 6-3
6.2.2 Module Base Address Register (MBAR) ....................................................... 6-4
6.2.3 Reset Status Register (RSR) ........................................................................... 6-5
6.2.4 Software Watchdog Timer.............................................................................. 6-6
6.2.5 System Protection Control Register (SYPCR) ............................................... 6-8
6.2.6 Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9
6.2.7 Software Watchdog Service Register (SWSR)............................................... 6-9
6.2.8 PLL Clock Control for CPU STOP Instruction............................................ 6-10
6.2.9 Pin Assignment Register (PAR) ................................................................... 6-10
6.2.10 Bus Arbitration Control ................................................................................ 6-11
6.2.10.1 Default Bus Master Park Register (MPARK) .......................................... 6-11
6.2.10.1.1 Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12
6.2.10.1.2 Arbitration between Internal and External Masters
for Accessing Internal Resources ......................................................... 6-14
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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