Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller FQFP 208 (28x28) 32-Bit 90 MHz I/O number 16

MCF5307UM/D

Rev. 2.0, 08/2000

MCF5307 ColdFire

Integrated Microprocessor

User’s Manual

eescale S

emiconduct

, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

Summary of content (484 pages)

PAGE 1
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MCF5307 ColdFire® Integrated Microprocessor User’s Manual MCF5307UM/D Rev. 2.0, 08/2000 For More Information On This Product, Go to: www.freescale.
PAGE 2
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein.
PAGE 3
Freescale Semiconductor, Inc. Overview Part I: MCF5307 Processor Core Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Freescale Semiconductor, Inc...
PAGE 4
Freescale Semiconductor, Inc. 1 Part I Part I: MCF5307 Processor Core 2 ColdFire Core 3 Hardware Multiply/Accumulate (MAC) Unit 4 Local Memory 5 Debug Support Part II Freescale Semiconductor, Inc...
PAGE 5
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... About This Book Chapter 1 Overview 1.1 1.2 1.2.1 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.1.6 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.7.1 1.3.7.2 1.3.7.3 1.3.7.4 1.3.7.5 1.3.8 1.3.9 1.4 1.4.1 1.4.2 1.4.3 1.4.4 Features ............................................................................................................... 1-1 MCF5307 Features....................................
PAGE 6
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Part I MCF5407 Processor Core Freescale Semiconductor, Inc... Chapter 2 ColdFire Core 2.1 2.1.1 2.1.2 2.1.2.1 2.1.2.1.1 2.1.2.2 2.1.2.2.1 2.1.2.2.2 2.1.2.2.3 2.1.3 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.1.4 2.2.1.5 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5 2.2.2.6 2.3 2.4 2.4.1 2.4.2 2.5 2.6 2.6.1 2.7 2.7.1 2.7.2 2.7.3 2.7.4 vi Features and Enhancements........................................................................
PAGE 7
Freescale Semiconductor, Inc. CONTENTS Paragraph Number 2.7.5 2.8 2.8.1 2.8.2 Title Page Number Branch Instruction Execution Times ............................................................ Exception Processing Overview ....................................................................... Exception Stack Frame Definition................................................................ Processor Exceptions ....................................................................................
PAGE 8
Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 4.9.5 4.9.5.1 4.9.5.2 4.9.5.2.1 4.9.5.2.2 4.9.6 4.10 4.10.1 4.10.2 4.11 4.12 4.12.1 4.13 Title Page Number Memory Accesses for Cache Maintenance................................................... Cache Filling............................................................................................. Cache Pushes ............................................................................................
PAGE 9
Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 5.5.3.3.4 5.5.3.3.5 5.5.3.3.6 5.5.3.3.7 5.5.3.3.8 5.5.3.3.9 5.5.3.3.10 5.5.3.3.11 5.5.3.3.12 5.5.3.3.13 5.6 5.6.1 5.6.1.1 5.6.2 5.7 5.8 5.8.1 5.8.2 Title Page Number Write Memory Location (WRITE) ......................................................... Dump Memory Block (DUMP) .............................................................. Fill Memory Block (FILL) ...................................................
PAGE 10
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... Chapter 7 Phase-Locked Loop (PLL) 7.1 7.1.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 7.4.1 7.4.2 7.5 Overview............................................................................................................. PLL:PCLK Ratios........................................................................................... PLL Operation .................................................................
PAGE 11
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Chapter 9 Interrupt Controller Freescale Semiconductor, Inc... 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 Overview............................................................................................................. Interrupt Controller Registers ............................................................................. Interrupt Control Registers (ICR0–ICR9) ......................................................
PAGE 12
Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.4 11.4.1 11.4.2 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 11.4.4 11.4.4.1 11.4.4.2 11.4.4.3 11.4.4.4 11.4.4.5 11.4.4.6 11.4.5 11.4.5.1 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 Title Page Number Burst Page-Mode Operation ................................................................... 11-12 Continuous Page Mode...................................................................
PAGE 13
Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 12.4.3 12.4.4 12.4.5 12.4.6 12.5 12.5.1 12.5.2 12.5.2.1 12.5.2.2 12.5.3 12.5.3.1 12.5.3.2 12.5.4 12.5.4.1 12.5.4.2 12.5.4.3 12.5.5 Title Page Number Byte Count Registers (BCR0–BCR3)........................................................... 12-7 DMA Control Registers (DCR0–DCR3)...................................................... 12-8 DMA Status Registers (DSR0–DSR3) ..............................................
PAGE 14
Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.3.10 14.3.11 14.3.12 14.3.13 14.3.14 14.4 14.5 14.5.1 14.5.1.1 14.5.1.2 14.5.1.2.1 14.5.1.2.2 14.5.2 14.5.2.1 14.5.2.2 14.5.2.3 14.5.3 14.5.3.1 14.5.3.2 14.5.3.3 14.5.4 14.5.5 14.5.5.1 14.5.5.2 14.5.5.3 14.5.6 14.5.6.1 Title Page Number UART Clock-Select Registers (UCSRn)...................................................... 14-8 UART Command Registers (UCRn) ...........
PAGE 15
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Part IV Hardware Interface Freescale Semiconductor, Inc... Chapter 16 Mechanical Data 16.1 16.2 16.3 16.4 Package ............................................................................................................. Pinout ................................................................................................................ Mechanical Diagram.....................................................................
PAGE 16
Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc... Paragraph Number 17.5.5.3 17.5.6 17.5.7 17.5.8 17.6 17.6.1 17.6.2 17.6.3 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.8 17.8.1 17.9 17.9.1 17.9.2 17.9.3 17.9.4 17.10 17.10.1 17.10.2 17.11 17.12 17.12.1 17.12.2 17.13 17.13.1 17.13.2 17.13.3 17.13.4 17.13.5 17.14 17.14.1 17.14.2 17.14.3 17.14.4 17.14.5 xvi Title Page Number D[6:5]—Port Size Configuration (PS_CONFIG[1:0]) ...........................
PAGE 17
Freescale Semiconductor, Inc. CONTENTS Paragraph Number Title Page Number Freescale Semiconductor, Inc... Chapter 18 Bus Operation 18.1 18.2 18.3 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 18.4.7 18.4.7.1 18.4.7.2 18.4.7.3 18.4.7.4 18.5 18.6 18.7 18.7.1 18.7.2 18.8 18.8.1 18.9 18.9.1 18.9.2 18.10 18.10.1 18.10.2 Features ............................................................................................................. 18-1 Bus and Control Signals ........................................
PAGE 18
Freescale Semiconductor, Inc. CONTENTS Paragraph Number 19.4.4 19.5 19.6 19.7 Title Page Number JTAG Bypass Register................................................................................ Restrictions ..................................................................................................... Disabling IEEE Standard 1149.1 Operation ................................................... Obtaining the IEEE Standard 1149.1..............................................................
PAGE 19
Freescale Semiconductor, Inc. ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 Title Page Number MCF5307 Block Diagram............................................................................................. 1-2 UART Module Block Diagram..................................................................................... 1-9 PLL Module ....
PAGE 20
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ILLUSTRATIONS Figure Page Title Number Number 5-10 Program Counter Breakpoint Register (PBR)............................................................. 5-14 5-11 Program Counter Breakpoint Mask Register (PBMR) ............................................... 5-14 5-12 Trigger Definition Register (TDR) ............................................................................. 5-15 5-13 BDM Serial Interface Timing ............................
PAGE 21
Freescale Semiconductor, Inc. ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number 6-9 6-10 6-11 6-12 6-13 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 Title Page Number Default Bus Master Register (MPARK) ..................................................................... 6-11 Round Robin Arbitration (PARK = 00)....................................................
PAGE 22
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ILLUSTRATIONS Figure Page Title Number Number 11-15 DRAM Control Register (DCR) (Synchronous Mode) ............................................ 11-19 11-16 DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20 11-17 DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22 11-18 Burst Read SDRAM Access ................................................................
PAGE 23
Freescale Semiconductor, Inc. ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number 14-10 14-11 14-12 14-13 14-14 14-15 14-17 14-16 14-18 14-19 14-20 14-21 14-22 14-23 14-24 14-25 14-26 14-27 15-1 15-2 15-3 16-1 16-2 16-3 17-1 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 Title Page Number UART Auxiliary Control Register (UACRn) ...........................................................
PAGE 24
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ILLUSTRATIONS Figure Page Title Number Number 18-19 Longword Read from an 8-Bit Port, External Termination...................................... 18-16 18-20 Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16 18-21 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17 18-22 Example of a Misaligned Word Transfer (32-Bit Port) ...........................
PAGE 25
Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 Title Page Number User-Level Registers................................................................................................... 1-14 Supervisor-Level Registers.........................................................................................
PAGE 26
Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 xxvi Title Page Number Processor Status Encoding............................................................................................ 5-4 BDM/Breakpoint Registers....................................................................
PAGE 27
Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 Title Page Number IRQPAR Field Descriptions ......................................................................................... 9-8 Chip-Select Module Signals .....................
PAGE 28
Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 11-34 11-35 11-36 11-37 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-5 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 15-1 15-2 15-3 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 xxviii Title Page Number DCR Initialization Values......................................................................................... 11-35 DACR Initialization Values...........................
PAGE 29
Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... Table Number 17-10 17-11 17-12 17-13 17-14 17-15 17-16 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 A-1 A-2 A-3 A-4 A-5 Title Page Number Data Pin Configuration ............................................................................................. 17-12 D7 Selection of CS0 Automatic Acknowledge ...............
PAGE 30
Freescale Semiconductor, Inc. TABLES Table Number xxx Page Number UART0 Control Registers............................................................................................ A-4 UART1 Control Registers............................................................................................ A-6 Parallel Port Memory Map........................................................................................... A-7 I2C Interface Memory Map..........................................................
PAGE 31
Freescale Semiconductor, Inc. About This Book Freescale Semiconductor, Inc... The primary objective of this user’s manual is to define the functionality of the MCF5307 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to be sure they are using the most recent version of the documentation.
PAGE 32
Organization Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... — Chapter 4, “Local Memory.” This chapter describes the MCF5307 implementation of the ColdFire V3 local memory specification. It consists of the two following major sections. • – Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization.
PAGE 33
Freescale Semiconductor, Inc. • Organization Part III, “Peripheral Module,” describes the operation and configuration of the MCF5307 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II. Freescale Semiconductor, Inc... — Chapter 12, “DMA Controller Module,” provides an overview of the DMA controller module and describes in detail its signals and registers.
PAGE 34
Suggested Reading Freescale Semiconductor, Inc. This manual includes the following appendix: • Appendix A, “List of Memory Maps,” lists the entire address-map for MCF5307 memory-mapped registers. This manual also includes a glossary and an index. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture. Freescale Semiconductor, Inc...
PAGE 35
Freescale Semiconductor, Inc. Acronyms and Abbreviations Freescale Semiconductor, Inc... italics 0x0 Italics indicate variable command parameters. Book titles in text are set in italics. Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register.
PAGE 36
Freescale Semiconductor, Inc. Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Freescale Semiconductor, Inc...
PAGE 37
Freescale Semiconductor, Inc. Terminology and Notational Conventions Terminology and Notational Conventions Table ii shows notational conventions used throughout this document. Table ii Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition (example: NE for not equal) An Any address register n (example: A3 is address register 3) Register Specifications Freescale Semiconductor, Inc...
PAGE 38
Freescale Semiconductor, Inc.
PAGE 39
Freescale Semiconductor, Inc. Terminology and Notational Conventions Table ii Notational Conventions (Continued) Instruction Operand Syntax Condition Code Register Bit Names Carry N Negative V Overflow X Extend Z Zero Freescale Semiconductor, Inc... C About This Book For More Information On This Product, Go to: www.freescale.
PAGE 40
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Terminology and Notational Conventions xl MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 41
Freescale Semiconductor, Inc. Chapter 1 Overview Freescale Semiconductor, Inc... This chapter is an overview of the MCF5307 ColdFire processor. It includes general descriptions of the modules and features incorporated in the MCF5307. 1.
PAGE 42
Freescale Semiconductor, Inc. Features V3 COLDFIRE PROCESSOR COMPLEX Instruction Unit JTAG Branch Logic CCR IAG IC1 IC2 IED GeneralPurpose Registers A0–A7 31 Instruction Fetch Pipeline (IFP) Eight-Instruction FIFO Buffer 0 Operand Execution Pipeline (OEP) D0–D7 Freescale Semiconductor, Inc...
PAGE 43
Freescale Semiconductor, Inc. Features Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated using advanced process technologies. Freescale Semiconductor, Inc... The MCF5307 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and ColdFire customers in which development tools and customer code can be leveraged.
PAGE 44
MCF5307 Features Freescale Semiconductor, Inc. 1.2 MCF5307 Features The following list summarizes MCF5307 features: Freescale Semiconductor, Inc...
PAGE 45
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
PAGE 46
MCF5307 Features Freescale Semiconductor, Inc... • • • • • Freescale Semiconductor, Inc.
PAGE 47
Freescale Semiconductor, Inc. ColdFire Module Description 1.3 ColdFire Module Description The following sections provide overviews of the various modules incorporated in the MCF5307. 1.3.1 ColdFire Core The Version 4 ColdFire core consists of two independent and decoupled pipelines to maximize performance—the instruction fetch pipeline (IFP) and the operand execution pipeline (OEP). Freescale Semiconductor, Inc... 1.3.1.
PAGE 48
Freescale Semiconductor, Inc. ColdFire Module Description 1.3.1.5 8-Kbyte Unified Cache The MCF5307 architecture includes an 8-Kbyte unified cache. This four-way, set-associative cache provides pipelined, single-cycle access on cached instructions and operands. Freescale Semiconductor, Inc... As with all ColdFire caches, the cache controller implements a non-lockup, streaming design.
PAGE 49
Freescale Semiconductor, Inc. ColdFire Module Description UART Internal Channel Control Logic CTS Serial Communications Channel RTS RxD TxD System Integration Module (SIM) Interrupt Controller Interrupt Control Logic Programmable Clock Generation BCLKO or External clock (TIN) Figure 1-2. UART Module Block Diagram Freescale Semiconductor, Inc...
PAGE 50
Freescale Semiconductor, Inc. ColdFire Module Description short distances among several devices. The I2C can operate in master, slave, or multiple-master modes. 1.3.7 System Interface The MCF5307 processor provides a direct interface to 8-, 16-, and 32-bit FLASH, SRAM, ROM, and peripheral devices through the use of fully programmable chip selects and write enables. Support for burst ROMs is also included. Through the on-chip PLL, users can input a slower clock (16.
PAGE 51
Freescale Semiconductor, Inc. ColdFire Module Description 1.3.7.5 JTAG To help with system diagnostics and manufacturing testing, the MCF5307 processor includes dedicated user-accessible test logic that complies with the IEEE 1149.1a standard for boundary-scan testability, often referred to as the Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a standard. Freescale Semiconductor, Inc... 1.3.
PAGE 52
Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set RSTO PCLK PSTCLK CLKIN PLL CLKIN X 4 Divide by 2 Divide by 2, 3, or 4 BCLKO FREQ[1:0] RSTI DIVIDE[1:0] Freescale Semiconductor, Inc... Figure 1-3. PLL Module The PLL module’s three modes of operation are described as follows. • • • Reset mode—When RSTI is asserted, the PLL enters reset mode. At reset, the PLL asserts RSTO from the MCF5307.
PAGE 53
Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set control. The supervisor programming model provides access to the same registers as the user model, plus additional registers for configuring on-chip system resources, as described in Section 1.4.3, “Supervisor Registers.” Exceptions (including interrupts) are handled in supervisor mode. 1.4.1 Programming Model Figure 1-4 shows the MCF5307 programming model.
PAGE 54
Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set 1.4.2 User Registers The user programming model is shown in Figure 1-4 and summarized in Table 1-1. Table 1-1. User-Level Registers Freescale Semiconductor, Inc... Register Description Data registers (D0–D7) These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as index registers.
PAGE 55
Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set 1.4.4 Instruction Set The ColdFire instruction set supports high-level languages and is optimized for those instructions most commonly generated by compilers in embedded applications. Table 2-8 provides an alphabetized listing of the ColdFire instruction set opcodes, supported operation sizes, and assembler syntax.
PAGE 56
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Programming Model, Addressing Modes, and Instruction Set 1-16 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 57
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Part I MCF5307 Processor Core Intended Audience Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5307. It also describes the operation of the MCF5307 Contents • • • • Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the MCF5307.
PAGE 58
Freescale Semiconductor, Inc. Suggested Reading The following literature may be helpful with respect to the topics in Part I: • • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Acronyms and Abbreviations Table I-i contains acronyms and abbreviations are used in Part I. Freescale Semiconductor, Inc... Table I-i.
PAGE 59
Freescale Semiconductor, Inc. Table I-i. Acronyms and Abbreviated Terms (Continued) Freescale Semiconductor, Inc...
PAGE 60
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. I-xx MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 61
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5307. The chapter begins with a description of enhancements from the Version 2 (V2) ColdFire core, and then fully describes the V3 programming model as it is implemented on the MCF5307. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. 2.
PAGE 62
Freescale Semiconductor, Inc. Features and Enhancements 2.1.1 Clock-Multiplied Microprocessor Core The MCF5307 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. The frequency of the processor complex can be 2x, 3x, or 4x the external bus speed. Freescale Semiconductor, Inc...
PAGE 63
Freescale Semiconductor, Inc. Features and Enhancements Freescale Semiconductor, Inc... Instruction Fetch Pipeline IAG Instruction Address Generation IC1 Instruction Fetch Cycle 1 IC2 Instruction Fetch Cycle 2 IED Instruction Early Decode IB FIFO Instruction Buffer DSOC Decode & Select, Operand Fetch AGEX Address Generation, Execute Address [31:0] Data[31:0] Operand Execution Pipeline Figure 2-1. ColdFire Enhanced Pipeline 2.1.2.
PAGE 64
Freescale Semiconductor, Inc. Features and Enhancements For example, if an unconditional BRA instruction is detected, the IED calculates the target of the BRA instruction, and the IAG immediately begins fetching at the target address. Because of the decoupled nature of the two pipelines, the target instruction is available to the OEP immediately after the BRA instruction, giving it a single-cycle execution time.
PAGE 65
Freescale Semiconductor, Inc. Features and Enhancements Figure 2-2 shows basic functionality of the MAC. A full set of instructions are provided for signed and unsigned integers plus signed, fixed-point fractional input operands. Operand Y Operand X X Shift 0,1,-1 Freescale Semiconductor, Inc... +/- Accumulator Figure 2-2.
PAGE 66
Programming Model Freescale Semiconductor, Inc. On-chip breakpoint resources include the following: Freescale Semiconductor, Inc... • • • • • • Configuration/status register (CSR) Background debug mode (BDM) address attributes register (BAAR) Bus attributes and mask register (AATR) Breakpoint registers. These can be used to define triggers combining address, data, and PC conditions in single- or dual-level definitions.
PAGE 67
Freescale Semiconductor, Inc.
PAGE 68
Freescale Semiconductor, Inc. Programming Model 2.2.1.3 Stack Pointer (A7, SP) The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register. The initial value of A7 is loaded from the reset exception vector, address 0x0000.
PAGE 69
Freescale Semiconductor, Inc. Programming Model Table 2-1. CCR Field Descriptions (Continued) Bits Name 1 V Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand size; otherwise cleared. 0 C Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. • Freescale Semiconductor, Inc...
PAGE 70
Programming Model 15 14 13 Freescale Semiconductor, Inc. 12 11 10 9 8 7 6 System byte Field T Reset 0 — R/W R/W S M — 5 4 3 2 1 0 V C Condition code register (CCR) I P — X N Z 0 1 0 0 111 0 00 — — — — — R R/W R/W R R/W R/W R R/W R/W R/W R/W R/W Figure 2-5. Status Register (SR) Table 2-3 describes SR fields. Table 2-3. Status Field Descriptions Freescale Semiconductor, Inc... Bits Name Description 15 T Trace enable.
PAGE 71
Freescale Semiconductor, Inc. Integer Data Formats 2.2.2.4 Access Control Registers (ACR0–ACR1) The access control registers (ACR0–ACR1) define attributes for two user-defined memory regions. Attributes include definition of cache mode, write protect and buffer write enables. See Section 4.10.2, “Access Control Registers (ACR0–ACR1).” 2.2.2.5 RAM Base Address Register (RAMBAR) Freescale Semiconductor, Inc...
PAGE 72
Freescale Semiconductor, Inc. Organization of Data in Registers high-order portion does not change. The least significant bit (lsb) of all integer sizes is zero, the most-significant bit (msb) of a longword integer is 31, the msb of a word integer is 15, and the msb of a byte integer is 7. 31 30 1 0 msb lsb 31 7 Not used 31 0 msb Low order byte lsb Lower order word lsb 15 Not used msb Freescale Semiconductor, Inc...
PAGE 73
Freescale Semiconductor, Inc. Addressing Mode Summary organization is shown in Figure 2-9. 31 23 15 7 0 Longword 0x0000_0000 Word 0x0000_0000 Byte 0x0000_0000 Word 0x0000_0002 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003 Longword 0x0000_0004 Word 0x0000_0004 Byte 0x0000_0004 Word 0x0000_0006 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007 . Freescale Semiconductor, Inc... . .
PAGE 74
Instruction Set Summary Freescale Semiconductor, Inc. Table 2-5. ColdFire Effective Addressing Modes Addressing Modes Reg. Field Dn An 000 001 (An) (An)+ –(An) (d16, An) Category Data Memory Control Alterable reg. no. reg. no. X — — — — — X X 010 011 100 101 reg. no. reg. no. reg. no. reg. no. X X X X X X X X X — — X X X X X (d8, An, Xi) 110 reg. no.
PAGE 75
Freescale Semiconductor, Inc. Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction Operand Syntax Register Specifications An Any address register n (example: A3 is address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example: D5 is data register 5) Dy,Dx Source and destination data registers, respectively Freescale Semiconductor, Inc...
PAGE 76
Instruction Set Summary Freescale Semiconductor, Inc. Table 2-6. Notational Conventions (Continued) Instruction Operand Syntax Freescale Semiconductor, Inc...
PAGE 77
Freescale Semiconductor, Inc. Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction Operand Syntax P Branch prediction C Carry N Negative V Overflow X Extend Z Zero Freescale Semiconductor, Inc... 2.6.1 Instruction Set Summary Table 2-7 lists implemented user-mode instructions by opcode. Table 2-7. User-Mode Instruction Set Summary Instruction Operand Syntax Operand Size Operation ADD Dy,x y,Dx .L .
PAGE 78
Instruction Set Summary Freescale Semiconductor, Inc. Table 2-7. User-Mode Instruction Set Summary (Continued) Freescale Semiconductor, Inc... Instruction Operand Syntax Operand Size Operation CMPI y,Dx .L Destination – immediate data DIVS y,Dx y,Dx .W .L Dx /y → Dx {16-bit remainder; 16-bit quotient} Dx /y → Dx {32-bit quotient} Signed operation DIVU y,Dx Dy,x .W .
PAGE 79
Freescale Semiconductor, Inc. Instruction Set Summary Table 2-7. User-Mode Instruction Set Summary (Continued) Freescale Semiconductor, Inc... Instruction Operand Syntax Operand Size Operation MOVEM #,x y,# .L .L Listed registers → destination Source → listed registers MOVEQ #,Dx .B → .L Sign-extended immediate data → destination MSAC Ry,RxSF .L - (.W × .W) → .L .L - (.L × .L) → .L ACC – (Ry × Rx){<< 1 | >> 1} → ACC MSACL Ry,RxSF,y,Rw .L - (.W × .
PAGE 80
Instruction Timing Freescale Semiconductor, Inc. Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation TST y .B,.W,.L Set condition codes UNLK Ax Unsized Ax →SP; (SP) → Ax; SP + 4 → SP WDDATA y .B,.W,.L y →DDATA port 1 By default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode execution by setting CSR[UHE]. Table 2-8 describes supervisor-mode instructions. Table 2-8.
PAGE 81
Freescale Semiconductor, Inc. certain hardware resources within the processor are marked as “busy” for two clock cycles after the final DSOC cycle of the store instruction. If a subsequent store instruction is encountered within this two-cycle window, it is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive store operations is two cycles. The OEP can complete all memory accesses without memory causing any stall conditions.
PAGE 82
Freescale Semiconductor, Inc. Instruction Timing Table 2-10 lists execution times for MOVE.{B,W} instructions. Table 2-10. Move Byte and Word Execution Times Destination Freescale Semiconductor, Inc... Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).
PAGE 83
Freescale Semiconductor, Inc. Instruction Timing in the MAC execution pipeline. Table 2-12. MAC Move Execution Times Effective Address Freescale Semiconductor, Inc... Opcode Í Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # move.l ,ACC 1(0/0) — — — — — — 1(0/0) move.l ,MACSR 2(0/0) — — — — — — 2(0/0) move.l ,MASK 1(0/0) — — — — — — 1(0/0) move.l ACC,Rx 3(0/0) — — — — — — — move.l MACSR,CCR 3(0/0) — — — — — — — move.
PAGE 84
Instruction Timing Freescale Semiconductor, Inc. Table 2-14. Two-Operand Instruction Execution Times Effective Address Opcode Freescale Semiconductor, Inc... add.l Í ,Rx Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # 1(0/0) 4(1/0) 4(1/0) 4(1/0) 4(1/0) 5(1/0) 4(1/0) 1(0/0) add.l Dy, — 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — addi.l #imm,Dx 1(0/0) — — — — — — — addq.l #imm, 1(0/0) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 5(1/1) 4(1/1) — addx.
PAGE 85
Freescale Semiconductor, Inc. Instruction Timing Table 2-14. Two-Operand Instruction Execution Times (Continued) Effective Address Freescale Semiconductor, Inc... Opcode Í Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # mac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — — moveq #imm,Dx — — — — — — — 1(0/0) msac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — — msac.l Ry,Rx,ea,Rw — 5(1/0) 5(1/0) 5(1/0) 5(1/0) — — — muls.
PAGE 86
Freescale Semiconductor, Inc. Instruction Timing Table 2-15. Miscellaneous Instruction Execution Times (Continued) Effective Address Opcode Í Rn nop 3(0/0) pea Í — pulse Freescale Semiconductor, Inc... (An) stop #imm trap #imm (An)+ — -(An) — 2(0/1) — (d16,An) — — (d8,An,Xi*SF) — 3 2(0/1) (xxx).wl # — — — 3(0/1)4 2(0/1) — 1(0/0) — — — — — — — — — — — — — — 3(0/0)5 — — — — — — — 18(1/2) trapf 1(0/0) — — — — — — — trapf.
PAGE 87
Freescale Semiconductor, Inc. Exception Processing Overview if bcc is a forward branch && CCR[7] == 1 then the bcc is predicted as taken else if bcc is a backward branch then the bcc is predicted as taken Table 2-17 shows timing for Bcc instructions. Freescale Semiconductor, Inc... Table 2-17. Bcc Instruction Execution Times Opcode Predicted Correctly as Taken Predicted Correctly as Not Taken Predicted Incorrectly bcc 1(0/0) 1(0/0) 5(0/0) 2.
PAGE 88
Freescale Semiconductor, Inc. Exception Processing Overview Freescale Semiconductor, Inc... fixed-length stack frame for all exceptions. The exception type determines whether the program counter in the exception stack frame defines the address of the faulting instruction (fault) or of the next instruction to be executed (next). 4. The processor acquires the address of the first instruction of the exception handler. The exception vector table is aligned on a 1-Mbyte boundary.
PAGE 89
Freescale Semiconductor, Inc. Exception Processing Overview Table 2-18. Exception Vector Assignments (Continued) Stacked Program Counter 1 Vector Numbers Vector Offset (Hex) 62–63 0F8–0FC — 64–255 100–3FC Next 1 Assignment Reserved User-defined interrupts The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC of the instruction that immediately follows the instruction that caused the fault. Freescale Semiconductor, Inc...
PAGE 90
Freescale Semiconductor, Inc. Exception Processing Overview Table 2-20. Fault Status Encodings FS[3–0] 0000 0001-001x 0100 Freescale Semiconductor, Inc... 0101–011x Not an access or address error Reserved Error on instruction fetch Reserved 1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read 1101–111x • Definition Reserved Vector number—This 8-bit field, vector[7–0], defines the exception type.
PAGE 91
Freescale Semiconductor, Inc. Exception Processing Overview Table 2-21. MCF5307 Exceptions (Continued) Freescale Semiconductor, Inc... Exception Description Trace Exception ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this definition is the STOP instruction.
PAGE 92
Freescale Semiconductor, Inc. Exception Processing Overview Table 2-21. MCF5307 Exceptions (Continued) Freescale Semiconductor, Inc... Exception Description Reset Exception Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception priority; it provides for system initialization and recovery from catastrophic failure. When assertion of RSTI is recognized, current processing is aborted and cannot be recovered.
PAGE 93
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 3 Hardware Multiply/Accumulate (MAC) Unit This chapter describes the MCF5307 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). 3.
PAGE 94
Freescale Semiconductor, Inc. Overview Operand Y Operand X X Shift 0,1,-1 +/- Freescale Semiconductor, Inc... Accumulator Figure 3-1. ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints.
PAGE 95
Freescale Semiconductor, Inc. Overview These registers are described as follows: • • Freescale Semiconductor, Inc... • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.
PAGE 96
Freescale Semiconductor, Inc. Overview during the calculations. The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efficiently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for filling registers quickly with input data, filter coefficients, and output data.
PAGE 97
Freescale Semiconductor, Inc. MAC Instruction Execution Timings • • Freescale Semiconductor, Inc... • Two’s complement signed integer: In this format, an N-bit operand represents a number within the range -2(N-1) < operand < 2(N-1) - 1. The binary point is to the right of the least significant bit. Two’s complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 < operand < 2N - 1. The binary point is to the right of the least significant bit.
PAGE 98
Freescale Semiconductor, Inc. MAC Instruction Execution Timings Table 3-3 shows standard timings for MAC move instructions. Table 3-3. MAC Move Instruction Execution Times Effective Address Freescale Semiconductor, Inc... Opcode Í Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl # move.l ,ACC 1(0/0) — — — — — — 1(0/0) move.l ,MACSR 6(0/0) — — — — — — 6(0/0) move.l ,MASK 5(0/0) — — — — — — 5(0/0) move.l ACC,Rx 1(0/0) — — — — — — — move.
PAGE 99
Freescale Semiconductor, Inc. Chapter 4 Local Memory Freescale Semiconductor, Inc... This chapter describes the MCF5307 implementation of the ColdFire Version 3 local memory specification. It consists of two major sections. • • Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. Section 4.
PAGE 100
SRAM Operation Freescale Semiconductor, Inc. 0-modulo-32K location in the 4-Gbyte address space and configured to respond to either instruction or data accesses.Time-critical functions can be mapped into instruction the system stack. Other heavily-referenced data can be mapped into memory. The following summarizes features of the MCF5307 SRAM implementation: Freescale Semiconductor, Inc... • • • • • • 4-Kbyte SRAM, organized as 1024 x 32 bits Single-cycle throughput.
PAGE 101
Freescale Semiconductor, Inc. SRAM Programming Model Accesses are attempted in the following order: 1. SRAM 2. Cache (if space is defined as cacheable) 3. External access 4.4 SRAM Programming Model The SRAM programming model consists of RAMBAR. Freescale Semiconductor, Inc... 4.4.1 SRAM Base Address Register (RAMBAR) The SRAM modules are configured through the RAMBAR, shown in Figure 4-1. • • • • RAMBAR holds the base address of the SRAM.
PAGE 102
Freescale Semiconductor, Inc. SRAM Initialization Table 4-1. RAMBAR Field Description (Continued) Freescale Semiconductor, Inc... Bits Name Description 5–1 C/I, SC, SD, UC, UD Address space masks (ASn). These fields allow certain types of accesses to be masked, or inhibited from accessing the SRAM module. These bits are useful for power management as described in Section 4.6, “Power Management.” In particular, C/I is typically set.
PAGE 103
Freescale Semiconductor, Inc. SRAM Initialization out of internal SRAM or cache during DMA access. The ColdFire processor or an external emulator using the debug module can perform these initialization functions. 4.5.1 SRAM Initialization Code The code segment below initializes the SRAM. The code sets the base address of the SRAM at 0x2000_0000 and then initializes the RAM to zeros. Freescale Semiconductor, Inc... RAMBASE RAMVALID move.l movec.
PAGE 104
Power Management Freescale Semiconductor, Inc... loop: Freescale Semiconductor, Inc. move.l asr.l 24(a7),d4 #4,d4 ;load byte count ;divide by 16 to convert to loop count .align movem.l movem.l lea.l lea.l subq.l bne.b 4 (a0),#0xf #0xf,(a1) 16(a0),a0 16(a1),a1 #1,d4 loop ;force loop on 0-mod-4 address ;read 16 bytes from source ;store into RAM destination ;increment source pointer ;increment destination pointer ;decrement loop counter ;if done, then exit, else continue movem.l lea.
PAGE 105
Freescale Semiconductor, Inc. Cache Organization Cache Control External Bus Control Control Logic Control Data Array ColdFire Processor Core Directory Array Data Freescale Semiconductor, Inc... System Integration Module (SIM) Address Address/ Data Data Data Path Address Address Path Figure 4-2. Unified Cache Organization The cache supports operation of copyback, write-through, or cache-inhibited modes.
PAGE 106
Freescale Semiconductor, Inc. Cache Organization Way 0 Way 1 Way 2 Way 3 • • • • • • Line • • • • • • Set 0 Set 1 Set 126 Set 127 Cache Line Format Freescale Semiconductor, Inc... TAG V M Longword 0 Longword 1 Longword 2 Longword 3 Where: TAG—21-bit address tag V—Valid bit for line M—Modified bit for line Figure 4-3. Cache Organization and Line Format A set is a group of four lines (one from each level, or way), corresponding to the same index into the cache array. 4.8.
PAGE 107
Freescale Semiconductor, Inc. Cache Organization 4.8.2 The Cache at Start-Up As Figure 4-4 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines even though the cache may not contain the appropriate data for start up. Because reset and power-up do not invalidate cache lines automatically, the cache should be cleared explicitly by setting CACR[CINVA] before the cache is enabled (B). Freescale Semiconductor, Inc...
PAGE 108
Cache Organization Freescale Semiconductor, Inc. Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A:Cache population at start-up B:Cache after invalidation, C:Cache after loads in before it is enabled Way 0 D:First load in Way 1 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 At reset, cache contents are indeterminate; V and M may be set.
PAGE 109
Freescale Semiconductor, Inc. Cache Operation 4.9 Cache Operation Figure 4-5 shows the general flow of a caching operation. Address 31 11 10 Freescale Semiconductor, Inc...
PAGE 110
Cache Operation Freescale Semiconductor, Inc. be deallocated and replaced. First the cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to the next way. Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking. If CACR[HLCK] = 1, the replacement pointer is restricted to way 2 or 3.
PAGE 111
Freescale Semiconductor, Inc. Cache Operation Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to this normal operation occurs when all of the following conditions are true during a cache-inhibited read: • • • The cache-inhibited fill buffer bit, CACR[DNFB], is set. The access is an instruction read. The access is normal (that is, transfer type (TT) equals 0). Freescale Semiconductor, Inc...
PAGE 112
Cache Operation Freescale Semiconductor, Inc. cache if matching data is found. Otherwise, the data is read from memory and the cache is updated. When a line is being read from memory for either a write-through or copyback read miss, the longword within the line that contains the core-requested data is loaded first and the requested data is given immediately to the processor, without waiting for the three remaining longwords to reach the cache.
PAGE 113
Freescale Semiconductor, Inc. Cache Operation 3. ACR1 4. If an access does not hit in the RAMBAR or the ACRs, the default is provided for all accesses in CACR. Cache-inhibited write accesses bypass the cache and a corresponding external write is performed. Cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the following conditions are true: Freescale Semiconductor, Inc... • • • The cache-inhibited fill-buffer bit, CACR[DNFB], is set.
PAGE 114
Cache Operation Freescale Semiconductor, Inc. 4.9.3.2 Write Miss The cache controller handles processor writes that miss in the cache differently for write-through and copyback regions. Write misses to copyback regions cause the cache line to be read from system memory, as shown in Figure 4-6. 1. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line. Cache Line 0x0C 0x08 MCF5307 0x04 0x00 V=0 M=0 Freescale Semiconductor, Inc... X 2.
PAGE 115
Freescale Semiconductor, Inc. Cache Operation also written to external memory. The cache line state is unchanged. For copyback accesses, the cache controller updates the cache line and sets the M bit for the line. An external write is not performed and the cache line state changes to (or remains in) the modified state. 4.9.4 Cache Coherency The MCF5307 provides limited cache coherency support in multiple-master environments.
PAGE 116
Cache Operation Freescale Semiconductor, Inc. 4.9.5.2 Cache Pushes Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed in the push buffer while the new line is fetched from memory. After the bus transfer for the new line completes, the modified cache line is written back to memory and the push buffer is invalidated. 4.9.5.2.
PAGE 117
Freescale Semiconductor, Inc. Cache Operation another cache fill is required (for example, cache miss to process) during the continued instruction execution by the processor pipeline, the pipeline stalls until the push and store buffers are empty, then generate the required external bus transaction. Supervisor instructions, the NOP instruction, and exception processing synchronize the processor core and guarantee the push and store buffers are empty before proceeding.
PAGE 118
Cache Operation Freescale Semiconductor, Inc. Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A:Ways 0 and 1 are filled. Ways 2 and 3 are invalid. B:CACR[DHLCK] is set, locking ways 0 and 1. C:When a set in Way 2 is D:Write hits to ways 0 occupied, the set in way 3 and 1 update cache is used for a cacheable lines. access.
PAGE 119
Freescale Semiconductor, Inc. Cache Registers 4.10 Cache Registers This section describes the MCF5307 implementation of the Version 3 cache registers. 4.10.1 Cache Control Register (CACR) The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the MOVEC register instruction and can be read or written from the debug facility. A hardware reset clears CACR, which disables the cache; however, reset does not affect the tags, state information, or data in the cache.
PAGE 120
Cache Registers Freescale Semiconductor, Inc. Table 4-4. CACR Field Descriptions (Continued) Bits Freescale Semiconductor, Inc... 27 Name Description HLCK Half-cache lock mode 0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache allocates the way pointed at by the counter and then increments this counter modulo-4. 1 Half-cache operation.
PAGE 121
Freescale Semiconductor, Inc. Cache Registers NOTE: The SIM MBAR region should be mapped as cache-inhibited through an ACR. 31 Field 24 23 Address Base Reset 16 15 14 13 12 Address Mask Uninitialized R/W S 7 6 — 0 5 CM 4 3 — 2 1 W 0 — Uninitialized Write (R/W by debug module) Rc Freescale Semiconductor, Inc... E ACR0: 0x004; ACR1: 0x005 Figure 4-9. Access Control Register Format (ACRn) Table 4-5 describes ACRn fields. I Table 4-5.
PAGE 122
Freescale Semiconductor, Inc. Cache Management 4.11 Cache Management The cache can be enabled and configured by using a MOVEC instruction to access CACR. A hardware reset clears CACR, disabling the cache and removing all configuration information; however, reset does not affect the tags, state information, and data in the cache. Set CACR[CINVA] to invalidate the cache before enabling it. Freescale Semiconductor, Inc...
PAGE 123
Freescale Semiconductor, Inc. Cache Operation Summary move.l cmpi.l bne rts d0,a0 #4,d0 setloop ;set = 0, way = d0 ;flushed all the ways? The following CACR loads assume the default cache mode is copyback. CacheLoadAndLock: move.l movec #0xA1000100,d0; enable and invalidate cache ... d0,cacr ; ... in the CACR Freescale Semiconductor, Inc... The following code preloads half of the cache (4 Kbytes).
PAGE 124
Freescale Semiconductor, Inc. Cache Operation Summary Figure 4-11 shows the three possible cache line states and possible processor-initiated transitions for memory configured as copyback. Transitions are labeled with a capital letter indicating the previous state and a number indicating the specific case listed in Table 4-11. CI5—CINVA CI6—CPUSHL & DPI CI7—CPUSHL & DPI CV1—CPU read miss CV2—CPU read hit CV7—CPUSHL & DPI CI1—CPU read miss Freescale Semiconductor, Inc...
PAGE 125
Freescale Semiconductor, Inc. Cache Operation Summary Table 4-6. Cache Line State Transitions Current State Access Invalid (V = 0) Freescale Semiconductor, Inc... Valid (V = 1, M = 0) Modified (V = 1, M = 1) Read miss (C,W)I1 Read line from memory and update cache; supply data to processor; go to valid state. (C,W)V1 Read new line from memory and update cache; supply data to processor; stay in valid state.
PAGE 126
Freescale Semiconductor, Inc. Cache Operation Summary The following tables present the same information as Table 4-6, organized by the current state of the cache line. In Table 4-7 the current state is invalid. Table 4-7. Cache Line State Transitions (Current State Invalid) Freescale Semiconductor, Inc... Access Response Read miss (C,W)I1 Read line from memory and update cache; supply data to processor; go to valid state.
PAGE 127
Freescale Semiconductor, Inc. Cache Initialization Code In the current state is modified. Table 4-9. Cache Line State Transitions (Current State Modified) Freescale Semiconductor, Inc... Access Response Read miss CD1 Push modified line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; go to valid state. Read hit CD2 Supply data to processor; stay in modified state.
PAGE 128
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Cache Initialization Code 4-30 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 129
Freescale Semiconductor, Inc. Chapter 5 Debug Support Freescale Semiconductor, Inc... This chapter describes the Revision B enhanced hardware debug support in the MC5307. This revision of the ColdFire debug architecture encompasses the earlier revision. 5.1 Overview The debug module is shown in Figure 5-1. High-speed local bus ColdFire CPU Core Debug Module Control BKPT Trace Port PST[3:0], DDATA[3:0] PSTCLK Communication Port DSCLK, DSI, DSO Figure 5-1.
PAGE 130
Signal Description Freescale Semiconductor, Inc. The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based on feedback from customers and third-party developers, enhancements have been added to succeeding generations of ColdFire cores.
PAGE 131
Freescale Semiconductor, Inc. Real-Time Trace Support Figure 5-2 shows PSTCLK timing with respect to PST and DDATA. PSTCLK PST or DDATA Figure 5-2. PSTCLK Timing Freescale Semiconductor, Inc... 5.3 Real-Time Trace Support Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system.
PAGE 132
Real-Time Trace Support Freescale Semiconductor, Inc. Table 5-2. Processor Status Encoding PST[3:0] Freescale Semiconductor, Inc... Definition Hex Binary 0x0 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding. 0x1 0001 Begin execution of one instruction.
PAGE 133
Freescale Semiconductor, Inc. Programming Model Bytes are displayed in least-to-most-significant order. The processor captures only those target addresses associated with taken branches which use a variant addressing mode, that is, RTE and RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception vectors. Freescale Semiconductor, Inc...
PAGE 134
Programming Model Freescale Semiconductor, Inc. programming model by executing the WDEBUG instruction. Thus, the breakpoint hardware in the debug module can be accessed by the external development system using the debug serial interface or by the operating system running on the processor core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent.
PAGE 135
Freescale Semiconductor, Inc. Programming Model Table 5-3. BDM/Breakpoint Registers DRc[4–0] 0x00 0x01–0x04 Register Name Abbreviation Initial State Page CSR 0x0010_0000 p. 5-10 Configuration/status register — — — 0x05 BDM address attribute register Reserved BAAR 0x0000_0005 p. 5-9 0x06 Address attribute trigger register AATR 0x0000_0005 p. 5-7 0x07 Trigger definition register TDR 0x0000_0000 p. 5-14 0x08 Program counter breakpoint register PBR — p.
PAGE 136
Programming Model Freescale Semiconductor, Inc. Table 5-4. AATR Field Descriptions Freescale Semiconductor, Inc... Bits Name Description 15 RM Read/write mask. Setting RM masks R in address comparisons. 14–13 SZM Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons. 12–11 TTM Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons. 10–8 TMM Transfer modifier mask.
PAGE 137
Freescale Semiconductor, Inc. Programming Model 31 0 Field Address Reset — R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port using the RDMREG and WDMREG commands. ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the BDM port using the WDMREG command. DRc[4–0] 0x0D (ABLR); 0x0C (ABHR) Figure 5-6.
PAGE 138
Freescale Semiconductor, Inc. Programming Model Table 5-7. BAAR Field Descriptions Freescale Semiconductor, Inc... Bits Name Description 7 R Read/write 0 Write 1 Read 6–5 SZ Size 00 Longword 01 Byte 10 Word 11 Reserved 4–3 TT Transfer type. See the TT definition in Table 5-4. 2–0 TM Transfer modifier. See the TM definition in Table 5-4. 5.4.
PAGE 139
Freescale Semiconductor, Inc. Programming Model Table 5-8. CSR Field Descriptions Bit Freescale Semiconductor, Inc... 31–28 Name Description BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. BSTAT is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.
PAGE 140
Programming Model Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 5-8. CSR Field Descriptions (Continued) Bit Name 10 UHE User halt enable. Selects the CPU privilege level required to execute the HALT instruction. 0 HALT is a supervisor-only instruction. 1 HALT is a supervisor/user instruction. 9–8 BTB Branch target bytes. Defines the number of bytes of branch target address DDATA displays.
PAGE 141
Freescale Semiconductor, Inc. Programming Model Table 5-9 describes DBR fields. Table 5-9. DBR Field Descriptions Bits Name 31–0 Data Description Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger. Table 5-10 describes DBMR fields. Table 5-10. DBMR Field Descriptions Bits Freescale Semiconductor, Inc... 31–0 Name Mask Description Data breakpoint mask. The 32-bit mask for the data breakpoint trigger.
PAGE 142
Programming Model Freescale Semiconductor, Inc. 31 1 Field Program Counter Reset — 0 R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in Section 5.5.3.3, “Command Set Descriptions.” DRc[4–0] 0x08 Figure 5-10. Program Counter Breakpoint Register (PBR) Table 5-12 describes PBR fields. Freescale Semiconductor, Inc... Table 5-12.
PAGE 143
Freescale Semiconductor, Inc. Programming Model NOTE: The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13] before defining triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. Section Table 5-14., “TDR Field Descriptions,” describes how to handle multiple breakpoint conditions. Second-Level Trigger Freescale Semiconductor, Inc...
PAGE 144
Freescale Semiconductor, Inc. Background Debug Mode (BDM) Table 5-14. TDR Field Descriptions (Continued) Bits Name 28–22 12–6 EDx Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints. 28/12 EDLW Data longword. Entire processor’s local data bus. 27/11 EDWL Lower data word. 26/10 EDWU Upper data word. 25/9 EDLL Lower lower data byte.
PAGE 145
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Background Debug Mode (BDM) 2. A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 5.6.1, “Theory of Operation.” 3.
PAGE 146
Freescale Semiconductor, Inc. Background Debug Mode (BDM) DSI must meet the required input setup and hold timings and the DSO is specified as a delay relative to the rising edge of the processor clock. See Table 5-1. The development system serves as the serial communication channel master and must generate DSCLK. The serial channel operates at a frequency from DC to 1/5 of the processor frequency.
PAGE 147
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.2.1 Receive Packet Format The basic receive packet, Figure 5-14, consists of 16 data bits and 1 status bit. 16 15 0 S Data Field [15:0] Figure 5-14. Receive BDM Packet Table 5-15 describes receive BDM packet fields. Freescale Semiconductor, Inc... Table 5-15. Receive BDM Packet Field Description Bits Name 16 S Description Status. Indicates the status of CPU-generated messages listed below.
PAGE 148
Freescale Semiconductor, Inc. Background Debug Mode (BDM) Table 5-17. BDM Command Summary Freescale Semiconductor, Inc... Command Mnemonic Read A/D register RAREG/ Write A/D register WAREG/ Read memory location Description CPU State1 Section Command (Hex) Read the selected address or data register and return the results through the serial interface. Halted 5.5.3.3.1 0x218 {A/D, Reg[2:0]} Write the data operand to the specified address or data register. Halted 5.5.3.3.
PAGE 149
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 15 10 Operation 9 8 0 R/W 7 6 5 4 3 Op Size 0 0 A/D 2 0 Register Extension Word(s) Figure 5-16. BDM Command Format Table 5-18 describes BDM fields. Table 5-18. BDM Field Descriptions Freescale Semiconductor, Inc... Bit Name Description 15–10 Operation Specifies the command. These values are listed in Table 5-17. 9 0 Reserved 8 R/W Direction of operand transfer.
PAGE 150
Freescale Semiconductor, Inc. Background Debug Mode (BDM) COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL-RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED Freescale Semiconductor, Inc...
PAGE 151
Freescale Semiconductor, Inc. Background Debug Mode (BDM) • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is sent to the debug module during the final transfer.
PAGE 152
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.1 Read A/D Register (RAREG/RDREG) Read the selected address or data register and return the 32-bit result. A bus error response is returned if the CPU core is not halted. Command/Result Formats: 15 Command 14 13 12 11 0x2 10 9 8 7 0x1 Result 6 5 4 0x8 3 A/D 2 1 Register D[31:16] D[15:0] Freescale Semiconductor, Inc... Figure 5-18.
PAGE 153
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.2 Write A/D Register (WAREG/WDREG) The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: 15 14 13 12 11 0x2 10 9 8 7 0x0 6 5 4 0x8 3 A/D 2 1 0 Register D[31:16] D[15:0] Freescale Semiconductor, Inc... Figure 5-20.
PAGE 154
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.3 Read Memory Location (READ) Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command/Result Formats: 15 14 Byte 13 12 11 10 0x1 9 8 7 0x9 6 5 4 3 0x0 Command 2 1 0 0x0 A[31:16] A[15:0] Freescale Semiconductor, Inc...
PAGE 155
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.4 Write Memory Location (WRITE) Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
PAGE 156
Freescale Semiconductor, Inc. Background Debug Mode (BDM) Command Sequence: WRITE (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR Freescale Semiconductor, Inc... NEXT CMD "NOT READY" WRITE (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" MS DATA "NOT READY" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Figure 5-25.
PAGE 157
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.5 Dump Memory Block (DUMP) is used with the READ command to access large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. If an initial READ is not executed before the first DUMP, an illegal command response is returned. The DUMP command retrieves subsequent operands.
PAGE 158
Freescale Semiconductor, Inc. Background Debug Mode (BDM) Command Sequence: READ MEMORY LOCATION DUMP (B/W) ??? XXX "NOT READY" NEXT CMD RESULT XXX "ILLEGAL" READ MEMORY LOCATION DUMP (LONG) ??? Freescale Semiconductor, Inc... NEXT CMD "NOT READY" XXX "ILLEGAL" XXX BERR NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "NOT READY" NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD "NOT READY" Figure 5-27.
PAGE 159
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.6 Fill Memory Block (FILL) A FILL command is used with the WRITE command to access large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. The FILL command writes subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register after the memory write.
PAGE 160
Freescale Semiconductor, Inc. Background Debug Mode (BDM) Command Sequence: FILL FILL(LONG) (B/W) ??? MS DATA "NOT READY" XXX "ILLEGAL" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" XXX BERR Freescale Semiconductor, Inc... FILL(LONG) (B/W) FILL ??? DATA "NOT READY" WRITE MEMORY LOCATION XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Figure 5-29.
PAGE 161
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.7 Resume Execution (GO) The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes. If a GO command is issued and the CPU is not halted, the command is ignored.
PAGE 162
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.8 No Operation (NOP) NOP performs no operation and may be used as a null command where required. Command Formats: 15 12 11 8 0x0 0x0 7 4 0x0 3 0 0x0 Figure 5-32. NOP Command Format Command Sequence: Freescale Semiconductor, Inc... NOP ??? NEXT CMD "CMD COMPLETE" Figure 5-33.
PAGE 163
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.9 Synchronize PC to the PST/DDATA Lines (SYNC_PC) Freescale Semiconductor, Inc... The SYNC_PC command captures the current PC and displays it on the PST/DDATA outputs. After the debug module receives the command, it sends a signal to the ColdFire processor that the current PC must be displayed. The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of CSR[BTB].
PAGE 164
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.10 Read Control Register (RCREG) Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.
PAGE 165
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.11 Write Control Register (WCREG) The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats: 15 Command 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 0 Rc Result D[31:16] Freescale Semiconductor, Inc... D[15:0] Figure 5-38.
PAGE 166
Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.12 Read Debug Module Register (RDMREG) Read the selected debug module register and return the 32-bit result. The only valid register selection for the RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR clears the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.
PAGE 167
Freescale Semiconductor, Inc. Real-Time Debug Support 5.5.3.3.13 Write Debug Module Register (WDMREG) The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. Command Format: Figure 5-42.
PAGE 168
Freescale Semiconductor, Inc. Real-Time Debug Support 5.6.1 Theory of Operation Breakpoint hardware can be configured to respond to triggers in several ways. The response desired is programmed into TDR. As shown in Table 5-21, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses. Table 5-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response Freescale Semiconductor, Inc...
PAGE 169
Freescale Semiconductor, Inc. Real-Time Debug Support fetches a unique exception vector, 12, from the vector table. Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program-visible registers into a reserved memory area. Freescale Semiconductor, Inc...
PAGE 170
Freescale Semiconductor, Inc. Motorola-Recommended BDM Pinout • • Read/write address and data registers Read/write control registers For BDM commands that access memory, the debug module requests the processor’s local bus. The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus. Freescale Semiconductor, Inc..
PAGE 171
Freescale Semiconductor, Inc. Processor Status, DDATA Definition The CSR provides capabilities to display operands based on reference type (read, write, or both). Additionally, for certain change-of-flow branch instructions, another CSR field provides the capability to display {0x2, 0x3, 0x4} bytes of the target instruction address. For both situations, an optional PST value {0x8, 0x9, 0xB} provides the marker identifying the size and presence of valid data on the DDATA output.
PAGE 172
Freescale Semiconductor, Inc. Processor Status, DDATA Definition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Freescale Semiconductor, Inc... Instruction Operand Syntax PST/DDATA cmp.l y,Rx PST = 0x1, {PST = 0xB, DD = source operand} cmpi.l #imm,Dx PST = 0x1 divs.l y,Dx PST = 0x1, {PST = 0xB, DD = source operand} divs.w y,Dx PST = 0x1, {PST = 0x9, DD = source operand} divu.l y,Dx PST = 0x1, {PST = 0xB, DD = source operand} divu.
PAGE 173
Freescale Semiconductor, Inc. Processor Status, DDATA Definition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Freescale Semiconductor, Inc... Instruction Operand Syntax PST/DDATA movem.l #list,x PST = 0x1, {PST = 0xB, DD = destination},... 2 movem.l y,#list PST = 0x1, {PST = 0xB, DD = source},... 2 moveq #imm,Dx PST = 0x1 msac.l Ry,Rx PST = 0x1 msac.l Ry,Rx,ea,Rw PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} msac.
PAGE 174
Freescale Semiconductor, Inc. Processor Status, DDATA Definition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax PST/DDATA unlk Ax PST = 0x1, {PST = 0xB, DD = destination operand} wddata.b y PST = 0x4, {PST = 0x8, DD = source operand wddata.l y PST = 0x4, {PST = 0xB, DD = source operand wddata.w y PST = 0x4, {PST = 0x9, DD = source operand Freescale Semiconductor, Inc...
PAGE 175
Freescale Semiconductor, Inc. Processor Status, DDATA Definition Table 5-23. PST/DDATA Specification for Supervisor-Mode Instructions Instruction movec Operand Syntax Ry,Rc Freescale Semiconductor, Inc...
PAGE 176
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Processor Status, DDATA Definition 5-48 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 177
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Part II System Integration Module (SIM) Intended Audience Part II is intended for users who need to understand the interface between the ColdFire core processor complex, described in Part I, and internal peripheral devices, described in Part III.
PAGE 178
Freescale Semiconductor, Inc. includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. Suggested Reading The following literature may be helpful with respect to the topics in Part II: The I2C Bus Specification, Version 2.1 (January 2000) • Freescale Semiconductor, Inc... Acronyms and Abbreviations Table II-i contains acronyms and abbreviations are used in Part II. Table II-i.
PAGE 179
Freescale Semiconductor, Inc. Table II-i. Acronyms and Abbreviated Terms (Continued) Freescale Semiconductor, Inc... Term Meaning NOP No operation PCLK Processor clock PLL Phase-locked loop POR Power-on reset Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part II.
PAGE 180
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. II-iv MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 181
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 6 SIM Overview This chapter provides detailed operation information regarding the system integration module (SIM). It describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5307. 6.1 Features The SIM, shown in Figure 6-1, provides overall control of the bus and serves as the interface between the ColdFire core processor complex and the internal peripheral devices.
PAGE 182
Features Freescale Semiconductor, Inc. The following is a list of the key SIM features: • • Freescale Semiconductor, Inc...
PAGE 183
Freescale Semiconductor, Inc. Programming Model 6.2 Programming Model The following sections describe the registers incorporated into the SIM. 6.2.1 SIM Register Memory Map Freescale Semiconductor, Inc... Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM are memory-mapped registers offset from the MBAR address pointer defined in MBAR[BA]. This supervisor-level register is described in Section 6.2.2, “Module Base Address Register (MBAR).
PAGE 184
Programming Model Freescale Semiconductor, Inc. Table 6-1. SIM Registers (Continued) MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x04C Software watchdog timer (ICR0) [p. 9-3] Timer0 (ICR1) [p. 9-3] Timer1 (ICR2) [p. 9-3] I2C (ICR3) [p. 9-3] 0x050 UART0 (ICR4) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA1 (ICR7) [p. 9-3] 0x054 DMA2 (ICR8) [p. 9-3] DMA3 (ICR9) [p. 9-3] Reserved Freescale Semiconductor, Inc... 6.2.
PAGE 185
Freescale Semiconductor, Inc. Programming Model Table 6-2 describes MBAR fields. Freescale Semiconductor, Inc... Table 6-2. MBAR Field Descriptions Bits Field 31–12 BA 11–9 — 8 WP Description Base address. Defines the base address for a 4-Kbyte address range. Reserved, should be cleared. Write protect. Mask bit for write cycles in the MBAR-mapped register address range. 0 Module address range is read/write. 1 Module address range is read only. 7 — Reserved, should be cleared.
PAGE 186
Programming Model Freescale Semiconductor, Inc. Table 6-3 describes RSR fields. Freescale Semiconductor, Inc... Table 6-3. RSR Field Descriptions Bits Name 7 HRST 6 — 5 SWTR 4–0 — Description Hardware or system reset 1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the core processor to take a reset exception. All registers in internal peripherals and the SIM are reset. Reserved, should be cleared.
PAGE 187
Freescale Semiconductor, Inc. Programming Model Code in the watchdog timer interrupt handler polls SYPCR[SWTAVAL] to determine if SWT TA was needed. If so, execute code to identify bad address. Code enables software watchdog timer interrupt and SWTA functionality by writing SYPCR. Problem: 1. Watchdog timer times out due to unterminated bus NOTE: The watchdog timer IRQ should be set to the highest level in the system. Freescale Semiconductor, Inc... Software watchdog timer IRQ Timeout 2.
PAGE 188
Programming Model 1. 2. 3. 4. Freescale Semiconductor, Inc. Disable the software watchdog timer by clearing SYPCR[SWE]. Reset the counter by writing 0x55 and then 0xAA to SWSR. Update SYPCR[SWT,SWP]. Reenable the watchdog timer by setting SYPCR[SWE]. This can be done in step 3. 6.2.5 System Protection Control Register (SYPCR) Freescale Semiconductor, Inc... The SYPCR, Figure 6-5, controls the software watchdog timer, timeout periods, and software watchdog timer transfer acknowledge.
PAGE 189
Freescale Semiconductor, Inc. Programming Model Table 6-4. SYPCR Field Descriptions (Continued) Bits Name Description 2 SWTA Software watchdog transfer acknowledge enable 0 SWTA transfer acknowledge disabled 1 SWTA asserts transfer acknowledge enabled. After one timeout period of the unacknowledged assertion of the software watchdog timer interrupt, the software watchdog transfer acknowledge asserts, which allows the watchdog timer to terminate a bus cycle and allow the IACK to occur.
PAGE 190
Programming Model Freescale Semiconductor, Inc. 6.2.8 PLL Clock Control for CPU STOP Instruction The SIM contains the PLL clock control register, which is described in detail in Section 7.2.4, “PLL Control Register (PLLCR).” PLLCR[ENBSTOP,PLLIPL] are significant to the operation of the SIM, and are described as follows: • Freescale Semiconductor, Inc... • PLLCR[ENBSTOP] must be set for the ColdFire CPU STOP instruction to be acknowledged.
PAGE 191
Freescale Semiconductor, Inc. Programming Model 6.2.10 Bus Arbitration Control This section describes the bus arbitration register and the four arbitration schemes. 6.2.10.1 Default Bus Master Park Register (MPARK) The MPARK, shown in Figure 6-9, determines the default bus master arbitration between internal transfers (core and DMA module) and between internal and external transfers to internal resources.
PAGE 192
Programming Model Freescale Semiconductor, Inc. Table 6-6. MPARK Field Descriptions (Continued) Bits Freescale Semiconductor, Inc... 3 Name Description SHOWDATA Enable internal register data bus to be driven on external bus. EARBCTRL must be set for this function to work. Section 6.2.10.1.2, “Arbitration between Internal and External Masters for Accessing Internal Resources,” describes the proper use of SHOWDATA. 0 Do not drive internal register data bus values to external bus.
PAGE 193
Freescale Semiconductor, Inc. • Note that the internal DMA has higher priority than the core if the internal DMA has its bandwidth BWC bits set to 000 (maximum bandwidth). Park on master core priority (PARK = 01)—The core retains bus mastership as long as it needs it. After it negates its internal bus request, the core does not have to rearbitrate for the bus unless the DMA module has requested the bus when it is idle.
PAGE 194
Programming Model • Freescale Semiconductor, Inc. Park on current master priority (PARK = 11)—The current bus master retains mastership as long as it needs the bus. The other device can become the bus master only when the bus is idle. For example, if the core is bus master out of reset, it retains mastership as long as it needs the bus. It loses mastership only when it negates its bus request signal and the DMA asserts its internal bus request signal.
PAGE 195
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... • Programming Model memories from responding to internal register transfers that go to the external bus. The AS signal and all chip-select-related strobe signals are not asserted. Do not immediately follow a cycle in which SHOWDATA is set with a cycle using fast termination.
PAGE 196
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Programming Model 6-16 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 197
Freescale Semiconductor, Inc. Chapter 7 Phase-Locked Loop (PLL) Freescale Semiconductor, Inc... This chapter describes configuration and operation of the phase-locked loop (PLL) module. It describes in detail the registers and signals that support the PLL implementation. 7.1 Overview The basic features of the MCF5307 PLL implementation are as follows: • • The PLL locks to the clock input (CLKIN) frequency.
PAGE 198
Freescale Semiconductor, Inc. PLL Operation 7.1.1 PLL:PCLK Ratios The specifications for the clocks in the PLL module are summarized in Table 0-1. Table 0-1. PLL Clock Specifications Symbol Freescale Semiconductor, Inc... — Description Frequency PLL lock time 2.2 mS with CLKIN running at 45 MHz CLKIN Input clock 16.67 MHz–45 MHz PCLK Internal processor clock 33.34 MHz–90 MHz (CLKIN x 2) PSTCLK Processor status clock 33.34 MHz–90 MHz (CLKIN x 2) BCLKO Output clock 16.
PAGE 199
Freescale Semiconductor, Inc. PLL Port List 7.2.4 PLL Control Register (PLLCR) The PLL control register (PLLCR), Figure 7-2, provides control over the PLL. 7 6 5 Field ENBSTOP 4 3 2 PLLIPL Reset 1 0 — 0000_0000 R/W R/W Address MBAR + 0x08 Figure 7-2. PLL Control Register (PLLCR) Freescale Semiconductor, Inc... Table 7-1 describes PLLCR bits. Table 7-1. PLLCR Field Descriptions Bit Name Description 7 ENBSTOP Enable CPU STOP instruction.
PAGE 200
Timing Relationships Freescale Semiconductor, Inc. Table 7-2. PLL Module Input SIgnals SIgnal Freescale Semiconductor, Inc... FREQ[1:0] Description Input bus indicating the CLKIN frequency range. FREQ[1:0] are multiplexed with D[3:2] and are sampled while RSTI is asserted. FREQ[1:0] must be correctly set for proper operation. These signals do not affect CLKIN frequency but are required to set up the analog PLL to handle the input clock frequency. 00 16.6–27.999 MHz 01 28–38.
PAGE 201
Freescale Semiconductor, Inc. Timing Relationships CLKIN PCLK PSTCLK BCLKO (/2) BCLKO (/3) Freescale Semiconductor, Inc... BCLKO (/4) NOTE: The clock signals are shown with edges aligned to show frequency relationships only. Actual signal edges have some skew between them. Figure 7-3. CLKIN, PCLK, PSTCLK, and BCLKO Timing 7.4.2 RSTI Timing Figure 7-4 shows PLL timing during reset.
PAGE 202
Freescale Semiconductor, Inc. PLL Power Supply Filter Circuit >80 CLKIN 100K CLKIN Cycle Lock Time CLKIN 30 BCLKO BCLKO (1/2 MODE) 20 BCLKO BCLKO (1/3 MODE) Freescale Semiconductor, Inc... 15 BCLKO BCLKO (1/4 MODE) PSTCLK RSTI D[7:0] D[7:0] latched RSTO Figure 7-4. Reset and Initialization Timing 7.5 PLL Power Supply Filter Circuit To ensure PLL stability, the power supply to the PLL power pin should be filtered using a circuit similar to the one in Figure 7-5.
PAGE 203
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 8 I2C Module This chapter describes the MCF5307 I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides extensive programming examples. 8.1 Overview I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices.
PAGE 204
Interface Features • • Freescale Semiconductor, Inc. Acknowledge bit generation/detection Bus-busy detection Figure 8-1 is a block diagram of the I2C module. Internal Bus IRQ Address Data Address Decode Data MUX I2C Data I/O Register (I2DR) I2C Address Register (IADR) Freescale Semiconductor, Inc...
PAGE 205
Freescale Semiconductor, Inc.2 I C System Configuration 8.3 I2C System Configuration The I2C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. For I2C compliance, all devices connected to these two signals must have open drain or open collector outputs. (There is no such requirement for inputs.) The logic AND function is exercised on both lines with external pull-up resistors. Out of reset, the I2C default is as slave receiver.
PAGE 206
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... I2C Protocol The slave whose address matches that sent by the master pulls SDA low at the ninth clock (D) to return an acknowledge bit. 3. Data transfer—When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master. Data can be changed only while SCL is low and must be held stable while SCL is high, as Figure 8-2 shows.
PAGE 207
Freescale Semiconductor, Inc. I2C Protocol determines the relative priority of competing devices. A device loses arbitration if it sends logic high while another sends logic low; it immediately switches to slave-receive mode and stops driving SDA. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. Freescale Semiconductor, Inc... 8.4.
PAGE 208
Freescale Semiconductor, Inc. Programming Model 8.5 Programming Model Table 8-1 lists the configuration registers used in the I2C interface. Table 8-1. I2C Interface Memory Map Freescale Semiconductor, Inc... MBAR Offset [31:24] [23:16] [15:8] 0x280 I2C address register (IADR) [p. 8-6] 0x284 I2C frequency divider register (IFDR) [p. 8-7] Reserved 0x288 I2C control register (I2CR) [p. 8-8] Reserved 0x28C I2C status register (I2SR) [p. 8-9] Reserved 0x290 I2C data I/O register (I2DR) [p.
PAGE 209
Freescale Semiconductor, Inc. Programming Model 8.5.2 I2C Frequency Divider Register (IFDR) The IFDR, Figure 8-6, provides a programmable prescaler to configure the clock for bit-rate selection. 7 Field 6 5 4 3 — 2 1 0 IC Reset 0000_0000 R/W Read/Write Address MBAR + 0x284 Freescale Semiconductor, Inc... Figure 8-6. I2C Frequency Divider Register (IFDR) Table 8-3 describes IFDR[IC]. Table 8-3. IFDR Field Descriptions Bits Name Description 7–6 — Reserved, should be cleared.
PAGE 210
Programming Model Freescale Semiconductor, Inc. 8.5.3 I2C Control Register (I2CR) The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern operation as a slave or a master. Field 7 6 5 4 3 2 IEN IIEN MSTA MTX TXAK RSTA Reset 1 0 — 0000_0000 R/W Read/Write Address MBAR + 0x288 Freescale Semiconductor, Inc... Figure 8-7. I2C Control Register (I2CR) Table 8-4 describes I2CR fields. Table 8-4.
PAGE 211
Freescale Semiconductor, Inc. Programming Model 8.5.4 I2C Status Register (I2SR) This I2SR contains bits that indicate transaction direction and status. Field 7 6 5 4 3 2 1 0 ICF IAAS IBB IAL — SRW IIF RXAK R/W R Reset R/W 1000_0001 R R R/W Address MBAR + 0x28C Figure 8-8. I2CR Status Register (I2SR) Freescale Semiconductor, Inc... Table 8-5 describes I2SR fields. Table 8-5. I2SR Field Descriptions Bits Name Description 7 ICF Data transferring bit.
PAGE 212
Freescale Semiconductor, Inc. I2C Programming Examples 8.5.5 I2C Data I/O Register (I2DR) In master-receive mode, reading the I2DR, Figure 8-9, allows a read to occur and initiates next byte data receiving. In slave mode, the same function is available after it is addressed. 7 6 5 4 3 Field D Reset 0000_0000 R/W 2 1 0 Read/Write Address MBAR + 0x290 Freescale Semiconductor, Inc... Figure 8-9. I2C Data I/O Register (I2DR) 8.
PAGE 213
Freescale Semiconductor, Inc. 2 I C Programming Examples and the first byte (the slave address) can be sent. The data written to the data register comprises the address of the desired slave and the lsb indicates the transfer direction. The free time between a STOP and the next START condition is built into the hardware that generates the START cycle.
PAGE 214
Freescale Semiconductor, Inc. I2C Programming Examples BTST.B #5,(A7)+;check the MSTA flag BEQ.S SLAVE;Branch if slave mode MOVE.B I2CR,-(A7);Push the address on stack BTST.B #4,(A7)+;check the mode flag BEQ.S RECEIVE;Branch if in receive mode MOVE.B I2SR,-(A7);Push the address on stack, BTST.B #0,(A7)+;check ACK from receiver BNE.B END;If no ACK, end of transmission TRANSMITMOVE.B DATABUF,-(A7);Stack data byte MOVE.B (A7)+, I2DR;Transmit next byte of data 8.6.
PAGE 215
Freescale Semiconductor, Inc. 2 I C Programming Examples 8.6.6 Slave Mode Freescale Semiconductor, Inc... In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS automatically.
PAGE 216
Freescale Semiconductor, Inc. I2C Programming Examples Clear IIF Y TX TX/Rx ? Master Mode? N Y RX Arbitration Lost? Freescale Semiconductor, Inc...
PAGE 217
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 9 Interrupt Controller This chapter describes the operation of the interrupt controller portion of the system integration module (SIM). It includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. 9.
PAGE 218
Freescale Semiconductor, Inc. Interrupt Controller Registers The SIM provides the following registers for managing interrupts: • • • • Freescale Semiconductor, Inc... • Each potential interrupt source is assigned one of the 10 interrupt control registers (ICR0–ICR9), which are used to prioritize the interrupt sources. The interrupt mask register (IMR) provides bits for masking individual interrupt sources.
PAGE 219
Freescale Semiconductor, Inc. Interrupt Controller Registers Table 9-2. Interrupt Control Registers (Continued) MBAR Offset Register Name 0x053 ICR7 DMA1 0x054 ICR8 DMA2 0x055 ICR9 DMA3 Freescale Semiconductor, Inc... Internal interrupts are programmed to a level and priority. Each internal interrupt has a unique ICR. Each of the 7 interrupt levels has 5 priorities, for a total of 35 possible priority levels, encompassing internal and external interrupts.
PAGE 220
Freescale Semiconductor, Inc. Interrupt Controller Registers NOTE: Assigning the same interrupt level and priority to multiple ICRs causes unpredictable system behavior. Table 9-4 shows possible priority schemes for internal and external sources of the MCF5307. The internal module interrupt source in this table can be any internal interrupt source programmed to the given level and priority. Freescale Semiconductor, Inc...
PAGE 221
Freescale Semiconductor, Inc. Interrupt Controller Registers Table 9-4. Interrupt Priority Scheme (Continued) Priority ICR Interrupt Level 16 Interrupt Source IL 4 17 100 11 100 10 Internal module xxx xxx 18 xxx xx External interrupt pin IRQ5 (programmed as IRQ4) 1xx 19 100 01 Internal module xxx 100 00 011 11 011 10 20 21 3 22 Freescale Semiconductor, Inc...
PAGE 222
Freescale Semiconductor, Inc. Interrupt Controller Registers Table 9-5 describes AVR fields. . Table 9-5. AVR Field Descriptions Bit Name 7–1 AVEC Autovector control. Determines whether the external interrupt at that level is autovectored. 0 Interrupting source returns vector during interrupt-acknowledge cycle. 1 SIM generates autovector during interrupt-acknowledge cycle. Freescale Semiconductor, Inc... 0 BLK Description Block address strobe (AS) for external AVEC access.
PAGE 223
Freescale Semiconductor, Inc. Interrupt Controller Registers 31 30 29 28 27 26 25 24 Field — Reset — R/W 23 22 21 20 19 18 17 16 DMA3 DMA2 1 1 Read-only (IPR); R/W (IMR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field DMA1 DMA0 UART1 UART0 I2C TIMER2 TIMER1 SWT EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 Reset 1111 1111 1111 R/W Read-only (IPR); R/W (IMR) Addr MBAR + 0x040 (IPR); + 0x044 (IMR) 1 1 — 1 — Freescale Semiconductor, Inc... Figure 9-4.
PAGE 224
Freescale Semiconductor, Inc. Interrupt Controller Registers Table 9-8. IRQPAR Field Descriptions Bits Name Description IRQPARn Configures the IRQ pin assignments and priorities IRQPARn External Pin IRQPARn = 0 IRQPARn = 1 IRQPAR2 IRQ5 Level 5 Level 4 IRQPAR1 IRQ3 Level 3 Level 6 IRQPAR0 IRQ1 Level 1 Level 2 4–0 — Reserved, should be cleared. Freescale Semiconductor, Inc... 7–5 9-8 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 225
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 10 Chip-Select Module This chapter describes the MCF5307 chip-select module, including the operation and programming model of the chip-select registers, which include the chip-select address, mask, and control registers. 10.
PAGE 226
Chip-Select Operation Freescale Semiconductor, Inc. Table 10-2.
PAGE 227
Freescale Semiconductor, Inc. • • Chip-Select Operation Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See Section 10.4.1.2, “Chip-Select Mask Registers (CSMR0–CSMR7).” Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, and automatic acknowledge generation features. See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).
PAGE 228
Chip-Select Operation Freescale Semiconductor, Inc. 10.3.1.1 8-, 16-, and 32-Bit Port Sizing Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).” Figure 10-1 shows the correspondence between data byte lanes and the external chip-select memory. Note that all lanes are driven, although unused lines are undefined.
PAGE 229
Freescale Semiconductor, Inc. Chip-Select Registers be programmed to continue decoding for a range of addresses after the CSMR0[V] is set, after which the global chip-select can be restored only by a system reset. 10.4 Chip-Select Registers Table 10-6Table 10-6 is the chip-select register memory map. Reading reserved locations returns zeros. Table 10-6. Chip-Select Registers MBAR Offset Freescale Semiconductor, Inc...
PAGE 230
Freescale Semiconductor, Inc. Chip-Select Registers Table 10-6. Chip-Select Registers (Continued) MBAR Offset [31:24] 0x0D8 [15:8] [7:0] Chip-select mask register—bank 7 (CSMR7) [p. 10-6] Reserved1 0x0DC 1 [23:16] Chip-select control register—bank 7 (CSCR7) [p. 10-8] Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. Freescale Semiconductor, Inc...
PAGE 231
Freescale Semiconductor, Inc. Chip-Select Registers . 31 16 15 Field 9 BAM — Reset 8 7 6 5 4 3 2 1 0 WP — AM C/I SC SD UC UD V Unitialized R/W R/W Addr 0x084 (CSMR0); 0x090 (CSMR1); 0x09C (CSMR2); 0x0A8 (CSMR3); 0x0B4 (CSMR4); 0x0C0 (CSMR5); 0x0CC (CSMR6); 0x0D8 (CSMR7) 0 Figure 10-3. Chip Select Mask Registers (CSMRn) Table 10-8 describes CSMR fields. Freescale Semiconductor, Inc... Table 10-8. CSMRn Field Descriptions Bits Name Description 31–16 BAM Base address mask.
PAGE 232
Freescale Semiconductor, Inc. Chip-Select Registers 10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7) Each chip-select control register, Figure 10-4, controls the auto acknowledge, external master support, port size, burst capability, and activation of each chip select. Note that to support the global chip select, CS0, the CSCR0 reset values differ from the other CSCRs. CS0 allows address decoding for boot ROM before system initialization.
PAGE 233
Freescale Semiconductor, Inc. Chip-Select Registers Table 10-9. CSCRn Field Descriptions Bits 3 Name Description BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CSn. 0 Break data larger than the specified port size into individual port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.
PAGE 234
Chip-Select Registers Freescale Semiconductor, Inc. move.w D0,CSAR2 move.w move.w #0x0538,D0 D0,CSCR2 ;CSCR2 = 1 wait state, AA=1, PS=32-bit, BEM=1, ;BSTR=1, BSTW=1 move.l move.l #0x001F0001,D0 D0,CSMR2 ;Address range from 0x00200000 to 0x003FFFFF ;WP,EM,C/I,SC,SD,UC,UD=0; V=1 Freescale Semiconductor, Inc... ; Program Chip Select 1 Registers move.w move.w #0x0000,D0 D0,CSAR1 ;CSAR1 base addresses 0x00000000 (to 0x001FFFFF) ;and 0x80000000 (to 0x801FFFFF) move.w move.
PAGE 235
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 11 Synchronous/Asynchronous DRAM Controller Module This chapter describes configuration and operation of the synchronous/asynchronous DRAM controller component of the system integration module (SIM). It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter consists of the two following parts: • • Section 11.
PAGE 236
Overview Freescale Semiconductor, Inc. 11.1.1 Definitions The following terminology is used in this chapter: • • Freescale Semiconductor, Inc... • A/SDRAM block—Any group of DRAM memories selected by one of the MCF5307 RAS[1:0] signals. Thus, the MCF5307 can support two independent memory blocks. The base address of each block is programmed in the DRAM address and control registers (DACR0 and DACR1).
PAGE 237
Freescale Semiconductor, Inc. DRAM Controller Operation • Freescale Semiconductor, Inc... • • • Control logic and state machine—Generates all DRAM signals, taking bus cycle characteristic data from the block logic, along with hit information to generate DRAM accesses. Handles refresh requests from the refresh counter. — DRAM control register (DCR)—Contains data to control refresh operation of the DRAM controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC].
PAGE 238
Asynchronous Operation Freescale Semiconductor, Inc. 11.3 Asynchronous Operation The DRAM controller supports asynchronous DRAMs for cost-effective systems. Typical access times for the DRAM controller interfacing to ADRAM are 4-3-3-3. The DRAM controller supports the following four asynchronous modes: Freescale Semiconductor, Inc... • • • • Non-page mode Burst page mode Continuous page mode Extended data-out mode In asynchronous mode, RAS and CAS always transition at the falling clock edge.
PAGE 239
Freescale Semiconductor, Inc. Asynchronous Operation 15 Field SO Reset 14 13 — NAM 12 11 10 RRA 0 9 8 0 RRP RC Uninitialized R/W R/W Address MBAR + 0x100 Figure 11-2. DRAM Control Register (DCR) (Asynchronous Mode) Table 11-3 describes DCR fields. Table 11-3. DCR Field Descriptions (Asynchronous Mode) Freescale Semiconductor, Inc... Bits Name Description 15 SO Synchronous operation. Selects synchronous or asynchronous mode.
PAGE 240
Asynchronous Operation Freescale Semiconductor, Inc. 31 18 17 16 Field BA Reset — Unitialized 15 14 13 12 11 10 RE — CAS RP 9 RNCN 0 8 7 6 RCD — EDO 5 4 PS 3 2 PM 1 0 — Unitialized R/W R/W Addr MBAR + 0x10C (DACR0); 0x110 (DACR1) Figure 11-3. DRAM Address and Control Registers (DACR0/DACR1) Table 11-4 describes DACRn fields. Freescale Semiconductor, Inc... Table 11-4. DACR0/DACR1 Field Description Bits Name Description 31–18 BA Base address.
PAGE 241
Freescale Semiconductor, Inc. Asynchronous Operation Freescale Semiconductor, Inc... Table 11-4. DACR0/DACR1 Field Description (Continued) Bits Name Description 5–4 PS Port size. Determines the port size of the associated DRAM block. For example, if two 16-bit wide DRAM components form one DRAM block, the port size is 32 bits. Programming PS allows the DRAM controller to execute dynamic bus sizing for associated accesses. 00 32-bit port 01 8-bit port 1x 16-bit port 3–2 PM Page mode.
PAGE 242
Asynchronous Operation Freescale Semiconductor, Inc. Table 11-5. DMR0/DMR1 Field Descriptions (Continued) Bits Name 6–1 AMx Description Address modifier masks. Determine which accesses can occur in a given DRAM block. 0 Allow access type to hit in DRAM 1 Do not allow access type to hit in DRAM Freescale Semiconductor, Inc...
PAGE 243
Freescale Semiconductor, Inc. Asynchronous Operation Table 11-6. Generic Address Multiplexing Scheme (Continued) Address Pin Row Address Column Address 20 20 19 21 21 20 22 22 21 23 23 22 24 24 23 25 25 24 Notes Relating to Port Sizes Freescale Semiconductor, Inc... Note the following: • • • • • Each MCF5307 address bit drives both a row address and a column address bit. As the user upgrades ADRAM, corresponding MCF5307 address bits must be connected.
PAGE 244
Asynchronous Operation Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 11-7.
PAGE 245
Freescale Semiconductor, Inc. Asynchronous Operation Freescale Semiconductor, Inc... Table 11-9. DRAM Addressing for 32-Bit Wide Memories MCF5307 Address Pin MCF5307 Address Bit Driven for RAS MCF5307 Address Bit Driven when CAS is Asserted 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 17 17 16 19 19 18 1 Mbyte 21 21 20 4 Mbytes 23 23 22 16 Mbytes 25 25 24 64 Mbytes Memory Size Base Memory Size of 64 Kbytes 256 Kbytes 11.3.3.
PAGE 246
Asynchronous Operation Freescale Semiconductor, Inc. Figure 11-6 shows a variation of the basic cycle. In this case, RCD is 1, so there are two clocks between RAS and CAS. Note that the address is multiplexed on the rising clock immediately before CAS is asserted. Because RNCN = 0, RAS and CAS are negated together. The next bus cycle is initiated, but because DACRn[RP] requires RAS to be precharged for two clocks, RAS is delayed for a clock in the bus cycle.
PAGE 247
Freescale Semiconductor, Inc. Asynchronous Operation BCLKO A[31:0] Row Column Column Column Column RAS[1] or [0] RCD = 0 CAS[3:0] CAS = 01 Freescale Semiconductor, Inc... DRAMW D[31:0] Figure 11-7. Burst Page-Mode Read Operation (4-3-3-3) Figure 11-8 shows the write operation with the same configuration. BCLKO A[31:0] Row Column Column Column Column RAS[1] or [0] RCD = 0 CAS[3:0] CAS = 01 DRAMW D[31:0] Figure 11-8. Burst Page-Mode Write Operation (4-3-3-3) 11.3.3.
PAGE 248
Asynchronous Operation Freescale Semiconductor, Inc. the next bus cycle are often available before the current cycle completes. The two addresses are compared at the end of the cycle to determine if the next address hits the same page. If so, RAS remains asserted. If not, or if no access is pending, RAS is precharged before the next bus cycle is active on the external bus. As a result, a page miss suffers no penalty. Single accesses not followed by a hit in the page look like non-page-mode accesses.
PAGE 249
Freescale Semiconductor, Inc. Asynchronous Operation BCLKO A[31:0] Row Column Column Page Hit RAS[1] or [0] Page Miss RCD = 0 CAS[3:0] CAS = 01 Freescale Semiconductor, Inc... DRAMW D[31:0] Bus Cycle 1 Bus Cycle 2 Figure 11-10. Write Hit in Continuous Page Mode 11.3.3.4 Extended Data Out (EDO) Operation EDO is a variation of page mode that allows the DRAM to continue driving data out of the device while CAS is precharging.
PAGE 250
Synchronous Operation Freescale Semiconductor, Inc. 11.3.3.5 Refresh Operation The DRAM controller supports CAS-before-RAS refresh operations that are not synchronized to bus activity. A special DRAMW pin is provided so refresh can occur regardless of the state of the processor bus. Freescale Semiconductor, Inc... When the refresh counter rolls over, it sets an internal flag to indicate that a refresh is pending.
PAGE 251
Freescale Semiconductor, Inc. Synchronous Operation Table 11-10. SDRAM Commands Freescale Semiconductor, Inc... Command Definition ACTV Activate. Executed before READ or WRITE executes; SDRAM registers and decodes row address. MRS Mode register set. NOP No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; RAS asserted. PALL Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is opened. READ Read access.
PAGE 252
Synchronous Operation Freescale Semiconductor, Inc. Table 11-11. Synchronous DRAM Signal Connections (Continued) Signal BCLKO Description Bus clock output. Connects to the CLK input of SDRAMs. EDGESEL Synchronous edge select. Provides additional output hold time for signals that interface to external SDRAMs. EDGESEL supports the three following modes for SDRAM interface signals: • Tied high. Signals change on the rising edge of BCLKO. • Tied low. Signals change on the falling edge of BCLKO.
PAGE 253
Freescale Semiconductor, Inc. Synchronous Operation BCLKO BCLKO Address/ Data VALID VALID VALID Address/ Data VALID A: Address and Data Timing with EDGESEL Tied High VALID VALID VALID B: Address and Data Timing with EDGESEL Tied Low Buffer Delay BCLKO Buffered Freescale Semiconductor, Inc... BCLKO Address/ Data VALID VALID VALID VALID C: Address and Data Timing with EDGESEL Tied to Buffered Clock Figure 11-14. Using EDGESEL to Change Signal Timing 11.4.
PAGE 254
Synchronous Operation Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 11-12. DCR Field Descriptions (Synchronous Mode) (Continued) Bits Name Description 12 COC Command on SDRAM clock enable (SCKE). Implementations that use external multiplexing (NAM = 1) must support command information to be multiplexed onto the SDRAM address bus. 0 SCKE functions as a clock enable; self-refresh is initiated by the DRAM controller through DCR[IS]. 1 SCKE drives command information.
PAGE 255
Freescale Semiconductor, Inc. Synchronous Operation Table 11-13 describes DACRn fields. Freescale Semiconductor, Inc... Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode) Bit Name 31–18 BA Base address register. With DCMR[BAM], determines the address range in which the associated DRAM block is located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM block.
PAGE 256
Synchronous Operation Freescale Semiconductor, Inc. Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode) (Continued) Bit Name Description IMRS Initiate mode register set (MRS) command. Setting IMRS generates a MRS command to the associated SDRAMs. In initialization, IMRS should be set only after all DRAM controller registers are initialized and PALL and REFRESH commands have been issued. After IMRS is set, the next access to an SDRAM block programs the SDRAM’s mode register.
PAGE 257
Freescale Semiconductor, Inc. Synchronous Operation Freescale Semiconductor, Inc... Table 11-14. DMR0/DMR1 Field Descriptions Bits Name Description 31–18 BAM Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various DRAM sizes. Mask bits need not be contiguous (see Section 11.5, “SDRAM Example.”) 0 The associated address bit is used in decoding the DRAM hit to a memory block. 1 The associated address bit is not used in the DRAM hit decode.
PAGE 258
Synchronous Operation Freescale Semiconductor, Inc. tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5307, which is not necessarily the SDRAM port size. For example, if two 1M x 16-bit SDRAMs together form a 2M x 32-bit memory, the port size is 32 bits. Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected. Table 11-15.
PAGE 259
Freescale Semiconductor, Inc. Synchronous Operation Table 11-19. MCF5307 to SDRAM Interface (8-Bit Port,13-Column Address Lines) MCF5307 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 16 15 14 13 12 11 10 9 19 21 23 25 0 1 2 3 4 5 6 7 8 18 20 22 24 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Table 11-20.
PAGE 260
Freescale Semiconductor, Inc. Synchronous Operation Table 11-24. MCF5307 to SDRAM Interface (16-Bit Port, 12-Column Address Lines) MCF5307 A16 A15 A14 A13 A12 A11 A10 Pins A9 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31 Row 16 15 14 13 12 11 10 9 18 20 22 24 Column 1 2 3 4 5 6 7 8 17 19 21 23 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 25 26 27 28 29 30 31 A10 A11 A12 A13 A14 A15 A16 A17 A18 Table 11-25.
PAGE 261
Freescale Semiconductor, Inc. Synchronous Operation Table 11-29. MCF5307 to SDRAM Interface (32-Bit Port, 11-Column Address Lines) MCF5307 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 24 25 26 27 28 29 30 31 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Table 11-30.
PAGE 262
Synchronous Operation Freescale Semiconductor, Inc. latency (SCAS assertion to data out), this value is also 2 BCLKO cycles. Notice that NOPs are executed until the last data is read. A PALL command is executed one cycle after the last data transfer. BCLKO A[31:0] Row Column Column Column Column SRAS tRCD = 2 Freescale Semiconductor, Inc... SCAS tEP DRAMW tCASL = 2 D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP READ NOP NOP PALL Figure 11-18.
PAGE 263
Freescale Semiconductor, Inc. Synchronous Operation BCLKO A[31:0] Row Column Column Column Column SRAS tRP SCAS tCASL = 2 tRWL Freescale Semiconductor, Inc... DRAMW D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP WRITE NOP PALL Figure 11-19. Burst Write SDRAM Access Accesses in synchronous burst page mode always cause the following sequence: 1. 2. 3. 4. 5. 6. command NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no NOP commands).
PAGE 264
Synchronous Operation • Freescale Semiconductor, Inc. Because of the nature of the internal CPU pipeline this condition does not occur often; however, the use of continuous page mode is recommended because it can provide a slight performance increase. Figure 11-20 shows two read accesses in continuous page mode. Note that there is no precharge between the two accesses. Also notice that the second cycle begins with a read operation with no ACTV command. BCLKO Row Freescale Semiconductor, Inc...
PAGE 265
Freescale Semiconductor, Inc. Synchronous Operation BCLKO Row A[31:0] Column Column SRAS SCAS tEP tRCD = 3 Freescale Semiconductor, Inc... DRAMW tCASL = 3 D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP WRITE NOP READ NOP NOP NOP PALL Figure 11-21. Synchronous, Continuous Page-Mode Access—Read after Write 11.4.4.5 Auto-Refresh Operation The DRAM controller is equipped with a refresh counter and control. This logic is responsible for providing timing and control to refresh the SDRAM.
PAGE 266
Synchronous Operation Freescale Semiconductor, Inc. BCLKO A[31:0] SRAS tRC = 6 tRCD = 2 SCAS Freescale Semiconductor, Inc... DRAMW RAS[0] or [1] PALL NOP REF NOP ACTV Figure 11-22. Auto-Refresh Operation 11.4.4.6 Self-Refresh Operation Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM.
PAGE 267
Freescale Semiconductor, Inc. Synchronous Operation 11.4.5 Initialization Sequence Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports this sequence with the following procedure: Freescale Semiconductor, Inc... 1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any action is taken on the SDRAMs. This is normally around 100 µs. 2. Initialize the DCR, DACR, and DMR in their operational configuration.
PAGE 268
SDRAM Example Freescale Semiconductor, Inc. The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the SDRAM address space generates the MRS command to that SDRAM. The address of the access should be selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed for the MRS command. The MRS access can be a read or write.
PAGE 269
Freescale Semiconductor, Inc. SDRAM Example 11.5.1 SDRAM Interface Configuration To interface this component to the MCF5307 DRAM controller, use the connection table that corresponds to a 32-bit port size with 8 columns (Table 11-26). Two pins select one of four banks when the part is functional. Table 11-33 shows the proper hardware hook-up. Table 11-33.
PAGE 270
Freescale Semiconductor, Inc. SDRAM Example Accessible Memory SDRAM Component Bank 0 Bank 1 512 Kbyte Bank 2 512 Kbyte 1 Mbyte Bank 3 512 Kbyte 1 Mbyte 512 Kbyte 1 Mbyte 512 Kbyte 1 Mbyte 512 Kbyte 512 Kbyte 512 Kbyte Figure 11-26. SDRAM Configuration Freescale Semiconductor, Inc... The DACRs should be programmed as shown in Figure 11-27.
PAGE 271
Freescale Semiconductor, Inc. SDRAM Example Table 11-35. DACR Initialization Values Bits Name Setting 2 PM 1 1–0 — Description Indicates continuous page mode Reserved. Don’t care. 11.5.4 DMR Initialization Freescale Semiconductor, Inc... In this example, again, only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank. In addition the SDRAM component is mapped only to readable and writable supervisor and user data. The DMRs have the following configuration.
PAGE 272
Freescale Semiconductor, Inc. SDRAM Example 11.5.5 Mode Register Initialization When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding MCF5307 address pins must be determined while being aware of masking requirements. Table 11-37 lists the desired initialization setting: Freescale Semiconductor, Inc... Table 11-37.
PAGE 273
Freescale Semiconductor, Inc. SDRAM Example 11.5.6 Initialization Code The following assembly code initializes the SDRAM example. Power-Up Sequence: move.w move.w move.l move.l move.l move.l #0x8026, d0 d0, DCR #0xFF880300, d0 d0, DACR0 #0x00740075, d0 d0, DMR0 //Initialize DCR //Initialize DACR0 //Initialize DMR0 Freescale Semiconductor, Inc... Precharge Sequence: move.l move.l move.l move.l #0xFF880308, d0 d0, DACR0 #0xBEADDEED, d0 d0, 0xFF880000 //Set DACR0[IP] //Write to memory location to init.
PAGE 274
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... SDRAM Example 11-40 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 275
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Part III Peripheral Module Intended Audience Part III describes the operation and configuration of the MCF5307 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II. Contents Part III contains the following chapters: • • • • Chapter 12, “DMA Controller Module,” provides an overview of the DMA controller module and describes in detail its signals and registers.
PAGE 276
Freescale Semiconductor, Inc. Acronyms and Abbreviations Table III-i describes acronyms and abbreviations used in Part III. Table III-i. Acronyms and Abbreviated Terms Freescale Semiconductor, Inc...
PAGE 277
Freescale Semiconductor, Inc. Table III-i. Acronyms and Abbreviated Terms (Continued) Freescale Semiconductor, Inc... Term Meaning PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part III.
PAGE 278
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. III-iv MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 279
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 12 DMA Controller Module This chapter describes the MCF5307 DMA controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. 12.1 Overview The direct memory access (DMA) controller module provides an efficient way to move blocks of data with minimal processor interaction.
PAGE 280
DMA Signal Description Freescale Semiconductor, Inc. 12.1.1 DMA Module Features Freescale Semiconductor, Inc...
PAGE 281
Freescale Semiconductor, Inc. DMA Transfer Overview 12.3 DMA Transfer Overview Freescale Semiconductor, Inc... The DMA module usually transfers data faster than the ColdFire core can under software control. The term ‘direct memory access’ refers to peripheral device’s ability to access system memory directly, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels.
PAGE 282
Freescale Semiconductor, Inc. DMA Controller Module Programming Model Write: Control Signals Memory DMA Data Control Signals Peripheral Read: Freescale Semiconductor, Inc... Control Signals Memory DMA Data Control Signals Peripheral Figure 12-3. Single-Address Transfers Any operation involving the DMA module follows the same three steps: 1. Channel initialization—Channel registers are loaded with control information, address pointers, and a byte-transfer count. 2.
PAGE 283
Freescale Semiconductor, Inc. DMA Controller Module Programming Model Table 12-2. Memory Map for DMA Controller Module Registers DMA Channel MBAR Offset 0 0x300 Source address register 0 (SAR0) [p. 12-6] 0x304 Destination address register 0 (DAR0) [p. 12-7] 0x308 DMA control register 0 (DCR0) [p. 12-8] Freescale Semiconductor, Inc... 0x30C 1 [31:24] [15:8] Byte count register 0 (BCR24BIT = 0) 1 [7:0] Reserved 0x30C Reserved Byte count register 0 (BCR24BIT = 1) 1 (BCR0) [p.
PAGE 284
Freescale Semiconductor, Inc. DMA Controller Module Programming Model Table 12-2. Memory Map for DMA Controller Module Registers (Continued) DMA Channel 3 MBAR Offset [31:24] [23:16] 0x3C0 Source address register 3 (SAR3) [p. 12-6] Destination address register 3 (DAR3) [p. 12-7] 0x3C8 Freescale Semiconductor, Inc... [7:0] 0x3C4 0x3CC 1 [15:8] DMA control register 3 (DCR3) [p.
PAGE 285
Freescale Semiconductor, Inc. DMA Controller Module Programming Model 12.4.2 Destination Address Registers (DAR0–DAR3) For dual-address transfers only, DARn, Figure 12-5, holds the address to which the DMA controller sends data. 31 0 Field DAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W R/W Address MBAR + 304, 0x344, 0x384, 0x3C4 Freescale Semiconductor, Inc... Figure 12-5.
PAGE 286
Freescale Semiconductor, Inc. DMA Controller Module Programming Model Bit 15 14 13 12 11 10 9 8 7 6 Field BCR Reset 0000_0000_0000_0000 5 4 3 2 1 0 R/W Addr MBAR + 0x30C, 0x34C, 0x38C, 0x3AC Figure 12-7. BCRn—BCR24BIT = 0 Freescale Semiconductor, Inc... DSR[DONE], shown in Figure 12-9, is set when the block transfer is complete.
PAGE 287
Freescale Semiconductor, Inc. DMA Controller Module Programming Model Table 12-3. DCRn Field Descriptions (Continued) Freescale Semiconductor, Inc... Bits Name Description 29 CS Cycle steal. 0 DMA continuously makes read/write transfers until the BCR decrements to 0. 1 Forces a single read/write transfer per request. The request may be internal by setting the START bit, or external by asserting DREQ. 28 AA Auto-align.
PAGE 288
Freescale Semiconductor, Inc. DMA Controller Module Programming Model Table 12-3. DCRn Field Descriptions (Continued) Freescale Semiconductor, Inc... Bits Name Description 16 START Start transfer. 0 DMA inactive 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one clock and is always read as logic 0. 15 AT AT is available only if BCR24BIT = 1. DMA acknowledge type.
PAGE 289
Freescale Semiconductor, Inc. DMA Controller Module Functional Description Table 12-4. DSRn Field Descriptions (Continued) Freescale Semiconductor, Inc... Bits Name Description 2 REQ Request 0 No request is pending or the channel is currently active. Cleared when the channel is selected. 1 The DMA channel has a transfer remaining and the channel is not selected. 1 BSY Busy 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
PAGE 290
Freescale Semiconductor, Inc. DMA Controller Module Functional Description to increment at the completion of a successful transfer. BCR decrements when an address transfer write completes for a single-address access (DCR[SAA] = 0) or when SAA = 1. 12.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) The DMA channel supports internal and external requests. A request is issued by setting DCR[START] or by asserting DREQ. Setting DCR[EEXT] enables recognition of external interrupts.
PAGE 291
Freescale Semiconductor, Inc. DMA Controller Module Functional Description • Dual-address write—The DMA controller drives the DAR value onto the address bus. If DCR[DINC] is set, DAR increments by the appropriate number of bytes at the completion of a successful write cycle. The BCR decrements by the appropriate number of bytes. DSR[DONE] is set when BCR reaches zero. If the BCR is greater than zero, another read/write transfer is initiated.
PAGE 292
Freescale Semiconductor, Inc. DMA Controller Module Functional Description is from memory to either a peripheral device or memory, the source address is the starting address of the data block. This can be any aligned byte address. In single-address mode, this data register is used regardless of transfer direction. Freescale Semiconductor, Inc... The DAR should contain the destination (write) address.
PAGE 293
Freescale Semiconductor, Inc. DMA Controller Module Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 CLKIN DREQ0 TM0 TT1 TT0 TS CS Freescale Semiconductor, Inc... TA R/W A[31:0] Read Write Figure 12-11. DREQ Timing Constraints, Dual-Address DMA Transfer Although Figure 12-11 does not show TM0 signaling a DMA acknowledgement, this signal can provide an external request acknowledge response, as shown in subsequent diagrams.
PAGE 294
Freescale Semiconductor, Inc. DMA Controller Module Functional Description CLKIN TS AS TIP A[31:0] R/W SIZ[1:0] Freescale Semiconductor, Inc... D[31:0] CSx TA DRAMW Precharge SRAS SCAS RAS[1:0] CAS[3:0] TT[1:0] 0 1 0 1 0 TM2 TM0 DREQ0 CPU DMA Read CPU DMA Write CPU Figure 12-12. Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer Figure 12-13 shows a single-address DMA transfer in which the peripheral is reading from memory.
PAGE 295
Freescale Semiconductor, Inc. DMA Controller Module Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 CLKIN DREQ0 TM0 TS A[31:0], SIZ[1:0] TIP R/W Freescale Semiconductor, Inc... TM2 TT0 TT1 CSx, AS OE, BE/BWE TA D[31:0] Figure 12-13. Single-Address DMA Transfer 12.5.4.2 Auto-Alignment Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCR[AA] must be set.
PAGE 296
Freescale Semiconductor, Inc. DMA Controller Module Functional Description 4. Repeat longwords until SAR = 0x00F0. 5. Read byte from 0x00F0—write byte, increment SAR. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. Freescale Semiconductor, Inc... 12.5.4.3 Bandwidth Control Bandwidth control makes it possible to force the DMA off the bus to allow access to another device.
PAGE 297
Freescale Semiconductor, Inc. Chapter 13 Timer Module Freescale Semiconductor, Inc... This chapter describes the configuration and operation of the two general-purpose timer modules (timer 0 and timer 1). It includes programming examples. 13.1 Overview The timer module incorporates two independent, general-purpose 16-bit timers, timer 0 and timer 1. The output of an 8-bit prescaler clocks each timer. There are two sets of registers, one for each timer.
PAGE 298
Freescale Semiconductor, Inc. General-Purpose Timer Units 13.1.1 Key Features Each general-purpose 16-bit timer unit has the following features: Freescale Semiconductor, Inc... • • • • • • • Maximum period of 5.
PAGE 299
Freescale Semiconductor, Inc. General-Purpose Timer Programming Model • • Reference compare—A timer can be configured to count up to a reference value, at which point TERn[REF] is set. If TMRn[ORI] is one, an interrupt is issued. If the free run/restart bit TMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running. Output mode—When a timer reaches the reference value selected by TMRn[OM], it can send an output signal on TOUTn.
PAGE 300
Freescale Semiconductor, Inc. General-Purpose Timer Programming Model Freescale Semiconductor, Inc... Table 13-2. TMRn Field Descriptions Bits Name Description 15–8 PS Prescaler value. The prescaler is programmed to divide the clock input (BCLKO/(16 or 1) or clock on TIN) by values from 1 (PS = 0000_0000) to 256 (PS = 1111_1111).
PAGE 301
Freescale Semiconductor, Inc. General-Purpose Timer Programming Model BCLKO is assumed to be the clock source. TIN cannot simultaneously function as a clocking source and as an input capture pin. 15 0 Field CAP (16-bit capture counter value) Reset 0000_0000_0000_0000 R/W Read only Address MBAR + 0x148 (TCR0); + 0x188 (TCR1) Figure 13-4. Timer Capture Register (TCR0/TCR1) Freescale Semiconductor, Inc... 13.3.
PAGE 302
Freescale Semiconductor, Inc. Code Example Table 13-3 describes TERn fields. Table 13-3. TERn Field Descriptions Bits Name Description 7–2 — 1 REF Output reference event. The counter has reached the TRRn value. Setting TMRn[ORI] enables the interrupt request caused by this event. Writing a one to REF clears the event condition. 0 CAP Capture event. The counter value has been latched into TCRn. Setting TMRn[CE] enables the interrupt request caused by this event.
PAGE 303
Freescale Semiconductor, Inc. Calculating Time-Out Values move.w TMR0,D0;save the contents of TMR0 while setting bset #0,D0 ;the 0 bit. This enables timer 0 and starts counting move.w D0, TMR0 ;load the value back into the register, setting TMR0[RST] T0_LOOP move.b TER0,D1 ;load TER0 and see if btst #1,D1 ;TER0[REF] has been set beq T0_LOOP addi.l #1,D2;Increment D2 cmp.l #5,D2;Did D2 reach 5? (i.e. timer ref has timed) beq T0_FINISH;If so, end timer0 example. Otherwise jump back.
PAGE 304
Freescale Semiconductor, Inc. Calculating Time-Out Values Table 13-5. Calculated Time-out Values (90-MHz Processor Clock) (Continued) Freescale Semiconductor, Inc... TMR[PS] TMR[CLK] = 10 (System Bus Clock/16) TMR[CLK] = 01 (System Bus Clock/1) Decimal Hex 45 MHz 30 MHz 22.5 MHz 45 MHz 30 MHz 22.5 MHz 6 6 0.16311 0.24467 0.32622 0.01019 0.01529 0.02039 7 7 0.18641 0.27962 0.37283 0.01165 0.01748 0.0233 8 8 0.20972 0.31457 0.41943 0.01311 0.01966 0.02621 9 9 0.
PAGE 305
Freescale Semiconductor, Inc. Calculating Time-Out Values Table 13-5. Calculated Time-out Values (90-MHz Processor Clock) (Continued) Freescale Semiconductor, Inc... TMR[PS] TMR[CLK] = 10 (System Bus Clock/16) TMR[CLK] = 01 (System Bus Clock/1) Decimal Hex 45 MHz 30 MHz 22.5 MHz 45 MHz 30 MHz 46 2E 1.09518 1.64277 2.19036 0.06845 0.10267 22.5 MHz 0.1369 47 2F 1.11848 1.67772 2.23696 0.06991 0.10486 0.13981 48 30 1.14178 1.71267 2.28357 0.07136 0.10704 0.14272 49 31 1.
PAGE 306
Freescale Semiconductor, Inc. Calculating Time-Out Values Table 13-5. Calculated Time-out Values (90-MHz Processor Clock) (Continued) Freescale Semiconductor, Inc... TMR[PS] TMR[CLK] = 10 (System Bus Clock/16) TMR[CLK] = 01 (System Bus Clock/1) Decimal Hex 45 MHz 30 MHz 22.5 MHz 45 MHz 30 MHz 22.5 MHz 86 56 2.02725 3.04087 4.05449 0.1267 0.19005 0.25341 87 57 2.05055 3.07582 4.1011 0.12816 0.19224 0.25632 88 58 2.07385 3.11078 4.1477 0.12962 0.19442 0.25923 89 59 2.
PAGE 307
Freescale Semiconductor, Inc. Calculating Time-Out Values Table 13-5. Calculated Time-out Values (90-MHz Processor Clock) (Continued) Freescale Semiconductor, Inc... TMR[PS] TMR[CLK] = 10 (System Bus Clock/16) TMR[CLK] = 01 (System Bus Clock/1) Decimal Hex 45 MHz 30 MHz 22.5 MHz 45 MHz 30 MHz 22.5 MHz 126 7E 2.95931 4.43897 5.91863 0.18496 0.27744 0.36991 127 7F 2.98262 4.47392 5.96523 0.18641 0.27962 0.37283 128 80 3.00592 4.50888 6.01184 0.18787 0.2818 0.
PAGE 308
Freescale Semiconductor, Inc. Calculating Time-Out Values Table 13-5. Calculated Time-out Values (90-MHz Processor Clock) (Continued) Freescale Semiconductor, Inc... TMR[PS] TMR[CLK] = 10 (System Bus Clock/16) TMR[CLK] = 01 (System Bus Clock/1) Decimal Hex 45 MHz 30 MHz 22.5 MHz 45 MHz 30 MHz 166 A6 3.89138 5.83707 7.78276 0.24321 0.36482 0.48642 167 A7 3.91468 5.87203 7.82937 0.24467 0.367 0.48934 168 A8 3.93799 5.90698 7.87597 0.24612 0.36919 0.49225 169 A9 3.
PAGE 309
Freescale Semiconductor, Inc. Calculating Time-Out Values Table 13-5. Calculated Time-out Values (90-MHz Processor Clock) (Continued) Freescale Semiconductor, Inc... TMR[PS] TMR[CLK] = 10 (System Bus Clock/16) TMR[CLK] = 01 (System Bus Clock/1) Decimal Hex 45 MHz 30 MHz 22.5 MHz 45 MHz 30 MHz 22.5 MHz 206 CE 4.82345 7.23517 9.6469 0.30147 0.4522 0.60293 207 CF 4.84675 7.27013 9.6935 0.30292 0.45438 0.60584 208 D0 4.87005 7.30508 9.74011 0.30438 0.45657 0.
PAGE 310
Freescale Semiconductor, Inc. Calculating Time-Out Values Table 13-5. Calculated Time-out Values (90-MHz Processor Clock) (Continued) Freescale Semiconductor, Inc... TMR[PS] TMR[CLK] = 10 (System Bus Clock/16) TMR[CLK] = 01 (System Bus Clock/1) Decimal Hex 45 MHz 30 MHz 22.5 MHz 45 MHz 30 MHz 22.5 MHz 246 F6 5.75552 8.63328 11.51103 0.35972 0.53958 0.71944 247 F7 5.77882 8.66823 11.55764 0.36118 0.54176 0.72235 248 F8 5.80212 8.70318 11.60424 0.36263 0.54395 0.
PAGE 311
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 14 UART Modules This chapter describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5307 and includes programming examples. All references to UART refer to one of these modules. 14.1 Overview The MCF5307 contains two independent UARTs. Each UART can be clocked by BCLKO, eliminating the need for an external crystal.
PAGE 312
Serial Module Overview Freescale Semiconductor, Inc. 14.2 Serial Module Overview The MCF5307 contains two independent UART modules, whose features are as follows: Freescale Semiconductor, Inc...
PAGE 313
Freescale Semiconductor, Inc. Register Descriptions Table 14-1. UART Module Programming Model MBAR Offset Freescale Semiconductor, Inc... [31:24] [23:16] UART0 UART1 0x1C0 0x200 UART mode registers1—(UMR1n) [p. 14-4], (UMR2n) [p. 14-6] — 0x1C4 0x204 (Read) UART status registers—(USRn) [p. 14-7] — (Write) UART clock-select register1—(UCSRn) [p. 14-8] — 0x1C8 0x1CC 0x1D0 0x208 0x20C 0x210 [15:8] [7:0] (Read) Do not access2 — (Write) UART command registers—(UCRn) [p.
PAGE 314
Register Descriptions Freescale Semiconductor, Inc. Table 14-1. UART Module Programming Model (Continued) MBAR Offset [31:24] [23:16] UART0 UART1 0x1E0– 0x1EC 0x220– Do not access2 0x22C — 0x1F0 0x230 UART interrupt vector register—(UIVRn) [p. 14-15] — 0x1F4 0x234 (Read) UART input port registers—(UIPn) [p. 14-15] — [15:8] [7:0] Freescale Semiconductor, Inc... (Write) Do not access2 — 0x1F8 0x238 (Read) Do not access2 — (Write) UART output port bit set command registers—(UOP1n3) [p.
PAGE 315
Freescale Semiconductor, Inc. Field 7 6 5 RxRTS RxIRQ/FFULL ERR Reset 4 2 1 PT 0 B/C 0000_0000 R/W Address 3 PM Register Descriptions R/W MBAR + 0x1C0 (UART0), 0x200 (UART1). After UMR1n is read or written, the pointer points to UMR2n. Figure 14-2. UART Mode Registers 1 (UMR1n) Table 14-2 describes UMR1n fields. Table 14-2. UMR1n Field Descriptions Bits Freescale Semiconductor, Inc... Name Description 7 RxRTS Receiver request-to-send.
PAGE 316
Freescale Semiconductor, Inc. Register Descriptions 14.3.2 UART Mode Register 2 (UMR2n) UART mode registers 2 (UMR2n) control UART module configuration. UMR2n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do not update the pointer. 7 Field 6 CM 5 4 TxRTS TxCTS Reset Freescale Semiconductor, Inc... 0 SB 0000_0000 R/W Address 3 R/W MBAR + 0x1C0, 0x200. After UMR1n is read or written, the pointer points to UMR2n.
PAGE 317
Freescale Semiconductor, Inc. Register Descriptions Freescale Semiconductor, Inc... Table 14-3. UMR2n Field Descriptions (Continued) Bits Name Description 3–0 SB Stop-bit length control. Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths of 9/16th to 2 bits are programmable for 6–8 bit characters. Lengths of 1 1/16th to 2 bits are programmable for 5-bit characters.
PAGE 318
Register Descriptions Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 14-4. USRn Field Descriptions (Continued) Bits Name Description 5 PE Parity error. Valid only if RxRDY = 1. 0 No parity error occurred. 1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received A/D bit. 4 OE Overrun error. Indicates whether an overrun occurs. 0 No overrun occurred.
PAGE 319
Freescale Semiconductor, Inc. Register Descriptions Table 14-5 describes UCSRn fields. Freescale Semiconductor, Inc... Table 14-5. UCSRn Field Descriptions Bits Name 7–4 RCS Receiver clock select. Selects the clock source for the receiver channel. 1101 Prescaled BCLKO 1110 TIN divided by 16 1111 TIN Description 3–0 TCS Transmitter clock select. Selects the clock source for the transmitter channel. 1101 Prescaled BCLKO 1110 TIN divided by 16 1111 TIN 14.3.
PAGE 320
Register Descriptions Freescale Semiconductor, Inc. Table 14-6. UCRn Field Descriptions (Continued) Bits Value Command Description 6–4 MISC Field (This field selects a single command.) 000 NO COMMAND — 001 RESET MODE Causes the mode register pointer to point to UMR1n. REGISTER POINTER 010 RESET RECEIVER Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes the receiver FIFO pointer. No other registers are altered.
PAGE 321
Freescale Semiconductor, Inc. Register Descriptions Table 14-6. UCRn Field Descriptions (Continued) Bits Value Command Freescale Semiconductor, Inc... 1–0 Description RC (This field selects a single command) 00 NO ACTION TAKEN Causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled.
PAGE 322
Register Descriptions Freescale Semiconductor, Inc. 7 0 Field TB Reset 0000_0000 R/W Write only Address MBAR + 0x1CC,0x20C Figure 14-8. UART Transmitter Buffer (UTB0) 14.3.8 UART Input Port Change Registers (UIPCRn) Freescale Semiconductor, Inc... The input port change registers (UIPCRn), Figure 14-9, hold the current state and the change-of-state for CTS.
PAGE 323
Freescale Semiconductor, Inc. Register Descriptions 7 1 Field — Reset 0 IEC 0000_0000 R/W Write only Address MBAR + 0x1D0 (UACR0), 0x210 (UACR1) Figure 14-10. UART Auxiliary Control Register (UACRn) Table 14-8 describes UACRn fields. Freescale Semiconductor, Inc... Table 14-8. UACRn Field Descriptions Bits Name 7–1 — 0 IEC Description Reserved, should be cleared. Input enable control. 0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
PAGE 324
Register Descriptions Freescale Semiconductor, Inc. Table 14-9. UISRn/UIMRn Field Descriptions Bits Freescale Semiconductor, Inc... 7 Name Description COS Change-of-state. 0 UIPCRn[COS] is not selected. 1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt. 6–3 — Reserved, should be cleared. 2 DB Delta break. 0 No new break-change condition to report. Section 14.3.5, “UART Command Registers (UCRn),” describes the RESET BREAK-CHANGE INTERRUPT command.
PAGE 325
Freescale Semiconductor, Inc. Register Descriptions 14.3.12 UART Interrupt Vector Register (UIVRn) The UIVRn, Figure 14-14, contain the 8-bit internal interrupt vector number (IVR). 7 0 Field IVR Reset 0000_1111 R/W R/W Address MBAR + 0x1F0 (UIVR0), 0x230 (UIVR1) Figure 14-14. UART Interrupt Vector Register (UIVRn) Freescale Semiconductor, Inc... Table 14-10 describes UIVRn fields. Table 14-10. UIVRn Field Descriptions Bits Name Description 7–0 IVR Interrupt vector.
PAGE 326
Freescale Semiconductor, Inc. UART Module Signal Definitions 7 1 Field — Reset 0 RTS 0000_0000 R/W Write only Addr UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0) Figure 14-16. UART Output Port Command Register (UOP1/UOP0) Table 14-12 describes UOP1 fields. Table 14-12. UOP1/UOP0 Field Descriptions Freescale Semiconductor, Inc... Bits Name Description 7–1 — Reserved, should be cleared. 0 RTS Output port parallel output.
PAGE 327
Freescale Semiconductor, Inc. UART Module Signal Definitions The interrupt level, priority, and auto-vectoring capability is programmed in SIM register ICR4 for UART0 and ICR5 for UART1. See Section 9.2.1, “Interrupt Control Registers (ICR0–ICR9).” Note that the UARTs can also automatically transfer data by using the DMA rather than interrupting the core. When UIMR[FFULL] is 1 and a receiver’s FIFO is full, it can send an interrupt to a DMA channel so the FIFO data can be transferred to memory.
PAGE 328
Freescale Semiconductor, Inc. Operation 14.5 Operation This section describes operation of the clock source generator, transmitter, and receiver. 14.5.1 Transmitter/Receiver Clock Source BCLKO serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to the UART. The clock generator cannot produce standard baud rates if BCLKO is used, so the 16-bit divider should be used. Freescale Semiconductor, Inc... 14.
PAGE 329
Freescale Semiconductor, Inc. Operation 14.5.1.2 Calculating Baud Rates The following sections describe how to calculate baud rates. 14.5.1.2.1 BCLKO Baud Rates When BCLKO is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UDUn and UDLn registers. Using a 45-MHz BCLKO, the baud-rate calculation is as follows: 45MHz Baudrate = -----------------------------------[ 32 × divider ] Freescale Semiconductor, Inc...
PAGE 330
Freescale Semiconductor, Inc. Operation UART0 Freescale Semiconductor, Inc...
PAGE 331
Freescale Semiconductor, Inc. Operation 14.5.2.1 Transmitting Freescale Semiconductor, Inc... The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a character, the UART sets USRn[TxRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on TxD. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The lsb is sent first.
PAGE 332
Freescale Semiconductor, Inc. Operation C1 in transmission C11 TxD C2 C3 C4 Break C6 Transmitter Enabled Freescale Semiconductor, Inc... USRn[TxRDY] internal module select W2 W W C11 C2 C3 Start break W W W C4 Stop break W W C5 not transmitted C6 CTS3 RTS4 Manually asserted by BIT-SET command Manually asserted 1 Cn = transmit characters 2 W = write 3 UMR2n[TxCTS] = 1 4 UMR2n[TxRTS] = 1 Figure 14-21. Transmitter Timing Diagram 14.5.2.
PAGE 333
Freescale Semiconductor, Inc. TxD C1 C2 C3 C4 C5 C6 Operation C7 C8 C6, C7, and C8 will be lost Receiver Enabled USRn[RxRDY] USRn[FFULL] Freescale Semiconductor, Inc... internal module select Status Data C5 will be lost (C1) Status Status Status Data Data Data Reset by command Overrun USRn[OE] RTS4 (C2) (C3) (C4) Manually asserted first time, automatically negated if overrun occurs UOP0[RTS] = 1 Automatically asserted when ready to receive Figure 14-22.
PAGE 334
Operation Freescale Semiconductor, Inc. The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. If the break begins in the middle of a character, the receiver places the damaged character in the Rx FIFO stack and sets the corresponding USRn error bits and USRn[RxRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RxRDY]. 14.5.2.
PAGE 335
Freescale Semiconductor, Inc. Operation available; therefore, overrun errors can be prevented by connecting RTS to the CTS input of the transmitting device. NOTE: The receiver can still read characters in the FIFO stack if the receiver is disabled. If the receiver is reset, the FIFO stack, RTS control, all receiver status bits, and interrupt requests are reset. No more characters are received until the receiver is reenabled. Freescale Semiconductor, Inc... 14.5.
PAGE 336
Operation Freescale Semiconductor, Inc. Rx Disabled RxD Input Disabled TxD Input CPU Tx Figure 14-24. Local Loop-Back Features of this local loop-back mode are as follows: Freescale Semiconductor, Inc... • • • • Transmitter and CPU-to-receiver communications continue normally in this mode. RxD input data is ignored TxD is held marking The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be. 14.5.3.
PAGE 337
Freescale Semiconductor, Inc. Operation a slave receives a block of data, its CPU disables the receiver and repeats the process.Functional timing information for multidrop mode is shown in Figure 14-26. Master Station A/D TxD ADD1 1 A/D A/D C0 ADD2 1 Transmitter Enabled Freescale Semiconductor, Inc...
PAGE 338
Operation Freescale Semiconductor, Inc. mode may still contain error detection and correction information. One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. 14.5.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 14.5.5.1 Read Cycles Freescale Semiconductor, Inc... The UART module responds to reads with byte data.
PAGE 339
Freescale Semiconductor, Inc. • Operation Interrupt handling—Consists of SIRQ (sheet 4), which is executed after the UART module generates an interrupt caused by a change-in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 14.5.6.
PAGE 340
Operation Freescale Semiconductor, Inc. ENABLE ENABLA SERIAL MODULE SINIT ANY ERRORS ? INITIATE: Y N CHANNEL INTERRUPTS ENABLE RECEIVER Freescale Semiconductor, Inc... CHK1 CALL CHCHK SAVE CHANNEL STATUS ASSERT REQUEST TO SEND SINITR RETURN Figure 14-27. UART Mode Programming Flowchart (Sheet 1 of 5) 14-30 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 341
Freescale Semiconductor, Inc. Operation CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE Freescale Semiconductor, Inc... ENABLE TRANSMITTER CLEAR STATUS WORD TxCHK N IS TRANSMITTER READY ? N Y WAITED TOO LONG ? Y SET TRANSMITTERNEVER-READY FLAG Y SET RECEIVERNEVER-READY FLAG N Y SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK N HAS CHARACTER BEEN RECEIVED ? N WAITED TOO LONG ? Y A B Figure 14-27. UART Mode Programming Flowchart (Sheet 2 of 5) Chapter 14.
PAGE 342
Freescale Semiconductor, Inc. Operation B A FRCHK RSTCHN HAVE FRAMING ERROR ? N Y RESTORE TO ORIGINAL MODE SET FRAMING ERROR FLAG PRCHK Freescale Semiconductor, Inc... DISABLE TRANSMITTER RETURN HAVE PARITY ERROR ? N Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER ? Y N SET INCORRECT CHARACTER FLAG B Figure 14-27. UART Mode Programming Flowchart (Sheet 3 of 5) 14-32 MCF5307 User’s Manual For More Information On This Product, Go to: www.
PAGE 343
Freescale Semiconductor, Inc. Operation INCH SIRQ ABRKI WAS IRQ CAUSED BY BEGINNING OF A BREAK ? Y N DOES CHANNEL A RECEIVER HAVE A CHARACTER ? N Y PLACE CHARACTER IN D0 CLEAR CHANGE-INBREAK STATUS BIT Freescale Semiconductor, Inc... ABRKI1 HAS END-OF-BREAK IRQ ARRIVED YET ? RETURN N Y CLEAR CHANGE-INBREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE Figure 14-27.
PAGE 344
Operation Freescale Semiconductor, Inc. OUTCH IS TRANSMITTER READY ? N Y Freescale Semiconductor, Inc... SEND CHARACTER TO TRANSMITTER RETURN Figure 14-27. UART Mode Programming Flowchart (Sheet 5 of 5) 14-34 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 345
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 15 Parallel Port (General-Purpose I/O) This chapter describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. It includes a code example for setting up the parallel port. 15.1 Parallel Port Operation The MCF5307 parallel port module has 16 signals, which are programmed as follows: • • • The pin assignment register (PAR) selects the function of the 16 multiplexed pins.
PAGE 346
Parallel Port Operation Freescale Semiconductor, Inc. Table 15-1. Parallel Port Pin Descriptions Pin Description PP[15:8]/ A[31:24] MSB of the address bus/parallel port. Programmed through PAR[15–8]. If a PAR bit is 0, the associated pin functions as a parallel port signal. If a bit is 1, the pin functions as an address bus signal. If all pins are address signals, as much as 4 Gbytes of memory space are available. TIP/PP7 Transfer-in-progress output/parallel port bit 7. Programmed through PAR[7].
PAGE 347
Freescale Semiconductor, Inc. • Parallel Port Operation PADAT can be written to anytime. A read from PADAT returns values of corresponding pins configured as general-purpose I/O in the PAR and designated as inputs by the PADDR. 15 0 Field PADAT Reset 0000_0000_0000_0000 R/W R/W Address Address MBAR+0x248 Freescale Semiconductor, Inc... Figure 15-3. Port A Data Register (PADAT) Table 15-3 shows relationships between PADAT bits and parallel port pins when PADAT is accessed.
PAGE 348
Parallel Port Operation Freescale Semiconductor, Inc. EQU EQU EQU EQU 0x00010000 MBARx+0x004 MBARx+0x244 MBARx+0x248 move.l movec move.w move.w move.w move.w move.b move.b #MBARx,D0 D0, MBAR #0x00FF,D0 D0,PAR #0x00F0,D0 D0,PADDR #0xA0,D0 D0,PADAT ;because MBAR is an internal register, MBARx is used as ;label for the memory map address ;set up the PAR. PP[7:0] set up as I/O ;set PP[7:4] as outputs; PP[3:0] as inputs ;0xA0 written into PADAT; PP[7:4] being outputs, ;PP[7:4] becomes 1010; i.e.
PAGE 349
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Part IV Hardware Interface Intended Audience Part IV is intended for hardware designers who need to know the functions and electrical characteristics of the MCF5407 interface. It includes a pinout, and both electrical and functional descriptions of the MCF5307 signals. It also describes how these signals interact to support the variety of bus operations shown in timing diagrams.
PAGE 350
Freescale Semiconductor, Inc. Suggested Reading The following literature may be helpful with respect to the topics in Part IV: • • IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Supplement to Standard Test Access Port and Boundary-Scan Architecture (1149.1) Acronyms and Abbreviations Table IV-i describes acronyms and abbreviations used in Part IV. Freescale Semiconductor, Inc... Table IV-i.
PAGE 351
Freescale Semiconductor, Inc. Table IV-i. Acronyms and Abbreviated Terms (Continued) Term Meaning Reduced instruction set computing Rx Receive SIM System integration module TAP Test access port TTL Transistor-to-transistor logic Tx Transmit Freescale Semiconductor, Inc... RISC Part IV. Hardware Interface For More Information On This Product, Go to: www.freescale.
PAGE 352
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. IV-iv MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 353
Freescale Semiconductor, Inc. Chapter 16 Mechanical Data Freescale Semiconductor, Inc... This chapter provides a function pin listing and package diagram for the MCF5307. See the website [http://www.motorola.com/coldfire] for any updated information. 16.1 Package The MCF5307 is assembled in a 208-pin, thermally enhanced plastic QFP package. 16.2 Pinout The MCF5307 pinout is detailed in the following tables, including the primary and secondary functions of multiplexed signals.
PAGE 354
Freescale Semiconductor, Inc. Pinout Table 16-1. Pins 1–52 (Left, Top-to-Bottom) (Continued) Freescale Semiconductor, Inc...
PAGE 355
Freescale Semiconductor, Inc. Pinout Table 16-1. Pins 1–52 (Left, Top-to-Bottom) (Continued) Pin No Name Alternate Function I/O Description Drive (mA) 48 GND — — Ground pin — 49 OE — O Output enable for chip selects 8 50 CS0 — O Chip select 8 51 CS1 — O Chip select 8 52 VCC — — Power input — Freescale Semiconductor, Inc... Table 16-2.
PAGE 356
Freescale Semiconductor, Inc. Pinout Table 16-2. Pins 53–104 (Bottom, Left-to-Right) (Continued) Freescale Semiconductor, Inc...
PAGE 357
Freescale Semiconductor, Inc. Pinout Table 16-3. Pins 105–156 (Right, Bottom-to-Top) (Continued) Pin Freescale Semiconductor, Inc...
PAGE 358
Freescale Semiconductor, Inc. Pinout Table 16-3. Pins 105–156 (Right, Bottom-to-Top) (Continued) Pin Freescale Semiconductor, Inc...
PAGE 359
Freescale Semiconductor, Inc. Pinout Table 16-4. Pins 157–208 (Top, Right-to-Left) (Continued) Pin Freescale Semiconductor, Inc...
PAGE 360
Mechanical Diagram Freescale Semiconductor, Inc. Table 16-4. Pins 157–208 (Top, Right-to-Left) (Continued) Pin Alternate Function I/O PP1 TT1 I/O Parallel port bit/Transfer type 8 PP0 TT0 I/O Parallel port bit/Transfer type 8 GND — — Ground pin — No Name 206 207 208 Description 16.3 Mechanical Diagram Freescale Semiconductor, Inc... Figure 16-1 is a mechanical diagram of the 208-pin QFP MCF5307. 16-8 MCF5307 User’s Manual For More Information On This Product, Go to: www.
PAGE 361
Freescale Semiconductor, Inc.
PAGE 362
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Case Drawing Figure 16-2. MCF5307 Case Drawing (General View) 16-10 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 363
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... View A: Three Places Case Drawing Section A-A: 160 Places Rotated 90° CW View B Figure 16-3. Case Drawing (Details) The dimensions in Figure 16-2 and Figure 16-3 are referenced in Table 16-5. Table 16-5. Dimensions Dimension (Millimeters) Reference Minimum Maximum A — 4.10 A1 0.25 0.50 A2 3.20 3.60 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 30.60 BSC Chapter 16.
PAGE 364
Freescale Semiconductor, Inc. Case Drawing Table 16-5. Dimensions (Continued) Dimension (Millimeters) Reference Minimum D1 28.00 BSC e 0.50 BSC E 30.60 BSC E1 28.00 BSC L 0.45 L1 Freescale Semiconductor, Inc... R1 16-12 Maximum 0.75 1.30 REF 0.08 — R2 0.08 0.25 S 0.20 — ϑ 0* 8* ϑ1 0* — ϑ2 5* 16* MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 365
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 17 Signal Descriptions This chapter describes MCF5307 signals. It includes an alphabetical listing of signals, showing multiplexing, whether it is an input or output to the MCF5307, the state at reset, and whether a pull-up resistor should be used. The following chapter, Chapter 18, “Bus Operation,” describes how these signals interact.
PAGE 366
Freescale Semiconductor, Inc. Overview TMS/BKPT Test Controller 2 2 Bus Interface Debug Module 4 4-Kbyte SRAM 32 DIV External to Internal Bus 8 2 8 4 Chip Selects 4 PST[3:0] DDATA[3:0] MAC 8-Kbyte Unified Cache Parallel Port1 Internal Bus Arbiter Interrupt Controller 2 1 Note: Parallel 2 I2C port pins (PPn) are multiplexed with other bus functions as shown. is a Philips proprietary interface Figure 17-1.
PAGE 367
Freescale Semiconductor, Inc. Overview Table 17-1. MCF5307 Signal Index Signal Name Abbreviation Function I/O Reset Pull-Up Page 17-7 Freescale Semiconductor, Inc... Section 17.2, “MCF5307 Bus Signals” Address A[31:0] 32-bit address bus. A[4:2] indicate the interrupt level for external interrupts. I/O Three state 17-7 Data D[31:0] Data bus. D[7:0] are loaded at reset for bus configuration.
PAGE 368
Freescale Semiconductor, Inc. Overview Table 17-1. MCF5307 Signal Index (Continued) Signal Name Abbreviation Function I/O Reset Frequency control PLL FREQ[1:0] Indicates CLKIN frequency range. I 17-15 Divide control PCLK to BCLKO DIVIDE[1:0] Indicates the BCLKO/PSTCLK ratio. I 17-15 17-15 Section 17.6, “Chip-Select Module Signals” Freescale Semiconductor, Inc... Pull-Up Page Chip selects[7:0] CS[7:0] Enables peripherals at programmed addresses; CS0 provides boot ROM selection.
PAGE 369
Freescale Semiconductor, Inc. Overview Table 17-1. MCF5307 Signal Index (Continued) Signal Name Parallel port Abbreviation PP[15:0] Function I/O Reset Pull-Up Page Interfaces with I/O; multiplexed with bus address and attribute signals. I/O Input 17-19 Section 17.12, “I2C Module Signals” 17-19 Serial clock line SCL Clock signal for I2C operation I/O Open drain Up 17-19 Serial data line SDA Serial data port for I2C operation I/O Open drain Up 17-19 17-20 Section 17.
PAGE 370
Freescale Semiconductor, Inc. Overview Table 17-2. MCF507 Alphabetical Signal Index (Continued) Abbreviation Signal Name I/O Page BCLKO Bus clock out Clock/reset O 17-13 BD Bus driven Bus arbitration O 17-13 BE[3:0]/BWE[3:0] Byte enable[3:0]/Byte write enable[3:0] Freescale Semiconductor, Inc...
PAGE 371
Freescale Semiconductor, Inc. MCF5307 Bus Signals Table 17-2. MCF507 Alphabetical Signal Index (Continued) Freescale Semiconductor, Inc...
PAGE 372
MCF5307 Bus Signals • • Freescale Semiconductor, Inc. A[31:24]—Pins are configured as address bits by setting corresponding PAR bits; they represent the most-significant address bus bits. As much as 4 Gbytes of memory are available when all of these pins are programmed as address signals. PP[15:8]—Pins are configured as parallel port signals by clearing corresponding PAR bits; these represent the most-significant parallel port bits. Freescale Semiconductor, Inc... 17.2.
PAGE 373
Freescale Semiconductor, Inc. MCF5307 Bus Signals = 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is transferred at offset 0x4 (SIZ[1:0] = 01). For aligned transfers larger than the port size, SIZ[1:0] behaves as follows: • • If bursting is used, SIZ[1:0] stays at the size of transfer. If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows the port size. Table 17-4. Bus Cycle Size Encoding Freescale Semiconductor, Inc...
PAGE 374
MCF5307 Bus Signals Freescale Semiconductor, Inc. external master access. This condition is indicated by the AM bit in the chip-select mask register (CSMR) being cleared. See Chapter 10, “Chip-Select Module.” 17.2.8 Transfer In Progress (TIP/PP7) The TIP/PP7 pin is programmed in the PAR to serve as the transfer-in-progress output or as a parallel port bits. The TIP output is asserted indicating a bus transfer is in progress.
PAGE 375
Freescale Semiconductor, Inc. MCF5307 Bus Signals Table 17-6. TM[2:0] Encodings for TT = 00 (Normal Access) (Continued) TM[2:0] Transfer Modifier 110 Supervisor code access 111 Reserved As shown in Table 17-7, if the DMA is bus master (TT = 01), TM[2:0] indicate the type of DMA access and provide the DMA acknowledgement information for channels 0 and 1. Freescale Semiconductor, Inc... NOTE: When TT= 01, the TM0 encoding is independent from TM[2:1] encoding. Table 17-7.
PAGE 376
Interrupt Control Signals Freescale Semiconductor, Inc. Table 17-10. TM[2:0] Encodings for TT = 11 (Interrupt Level) (Continued) TM[2:0] Transfer Modifier 010 Interrupt level 2 acknowledge 011 Interrupt level 3 acknowledge 100 Interrupt level 4 acknowledge 101 Interrupt level 5 acknowledge 110 Interrupt level 6 acknowledge 111 Interrupt level 7 acknowledge Freescale Semiconductor, Inc... 17.
PAGE 377
Freescale Semiconductor, Inc. Clock and Reset Signals 17.4.3 Bus Driven (BD) The MCF5307 asserts BD to indicate that it is the current master and is driving the bus. The MCF5307 behaves as follows: • • • Freescale Semiconductor, Inc... • If the MCF5307 is the bus master but is not using the bus, BD is asserted. If the MCF5307 loses mastership during a transfer, it completes the last transfer of the access, negates BD, and three-states all bus signals on the rising edge of BCLKO.
PAGE 378
Clock and Reset Signals Freescale Semiconductor, Inc. Table 17-11. Data Pin Configuration Pin Function D7 Auto-acknowledge configuration (AA_CONFIG) D[6:5] D4 Port size configuration (PS_CONFIG[1:0]) Address configuration (ADDR_CONFIG/D4) D[3:2] Frequency Control PLL (FREQ[1:0]) D[1:0] Divide Control (DIVIDE[1:0]) Freescale Semiconductor, Inc... 17.5.5.1 D[7:5Boot Chip-Select (CS0) Configuration D[7:5] determine defaults for the global chip select (CS0), the only chip select valid at reset.
PAGE 379
Freescale Semiconductor, Inc. Chip-Select Module Signals of memory if desired. ADDR_CONFIG is multiplexed with D4 and its configuration is sampled at reset as shown in Table 17-14. Table 17-14. D4/ADDR_CONFIG, Address Pin Assignment D4/ADDR_CONFIG PAR Configuration at Reset 0 PP[15:0], defaulted to inputs upon reset 1 A[31:24]/TIP/DREQ[1:0]/TM[2:0]/TT[1:0] Freescale Semiconductor, Inc... 17.5.
PAGE 380
DRAM Controller Signals Freescale Semiconductor, Inc. 17.6.1 Chip-Select (CS[7:0]) Each chip select can be programmed for a base address location and for masking addresses, port size and burst-capability indication, wait-state generation, and internal/external termination. Reset clears all chip select programming; CS0 is the only chip select initialized out of reset.
PAGE 381
Freescale Semiconductor, Inc. DMA Controller Module Signals 17.7.3 DRAM Write (DRAMW) The DRAM write signal (DRAMW) is asserted to signify that a DRAM write cycle is underway. A read bus cycle is indicated by the negation of DRAMW. 17.7.4 Synchronous DRAM Column Address Strobe (SCAS) The synchronous DRAM column address strobe (SCAS) is registered during synchronous mode to route directly to the SCAS signal of SDRAMs. Freescale Semiconductor, Inc... 17.7.
PAGE 382
Serial Module Signals Freescale Semiconductor, Inc. 17.8.1 DMA Request (DREQ[1:0]/PP[6:5]) The DMA request pins (DREQ[1:0]/PP[6:5]) can serve as the DMA request inputs or as two bits of the parallel port, as determined by individually programmable bits in the PAR. These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and memory by either channel 0 or 1 of the on-chip DMA.
PAGE 383
Freescale Semiconductor, Inc. Parallel I/O Port (PP[15:0]) 17.10.1 Timer Inputs (TIN[1:0]) TIN[1:0] can be programmed as clocks that cause events in the counter and prescalers. They can also cause captures on the rising edge, falling edge, or both edges. 17.10.2 Timer Outputs (TOUT1, TOUT0) The programmable timer outputs (TOUT1 and TOUT0) pulse or toggle on various timer events. Freescale Semiconductor, Inc... 17.11 Parallel I/O Port (PP[15:0]) This 16-bit bus is dedicated for general-purpose I/O.
PAGE 384
Debug and Test Signals Freescale Semiconductor, Inc. 17.13 Debug and Test Signals The signals in this section interface with external I/O to provide processor status signals. 17.13.1 Test Mode (MTMOD[3:0]) The test mode signals choose between multiplexed debug module and JTAG signals. If MTMOD0 is low, the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode.
PAGE 385
Freescale Semiconductor, Inc. Debug Module/JTAG Signals . Table 17-17. Processor Status Signal Encodings PST[3:0] Freescale Semiconductor, Inc...
PAGE 386
Freescale Semiconductor, Inc. Debug Module/JTAG Signals controller in test logic reset state immediately. Tying it to VDD causes the JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks. If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to the debug module. The maximum DSCLK frequency is 1/5 CLKIN. See Chapter 5, “Debug Support.” Freescale Semiconductor, Inc... 17.14.
PAGE 387
Freescale Semiconductor, Inc. Debug Module/JTAG Signals 17.14.5 Test Clock (TCK) Freescale Semiconductor, Inc... TCK is the dedicated JTAG test logic clock independent of the MCF5307 processor clock. Various JTAG operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground. Chapter 17. Signal Descriptions For More Information On This Product, Go to: www.
PAGE 388
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Debug Module/JTAG Signals 17-24 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 389
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 18 Bus Operation This chapter describes data-transfer operations, error conditions, bus arbitration, and reset operations. It describes transfers initiated by the MCF5307 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,” describes DRAM cycles. 18.
PAGE 390
Bus Characteristics Freescale Semiconductor, Inc. Table 18-1.
PAGE 391
Freescale Semiconductor, Inc. Data Transfer Operation 18.4 Data Transfer Operation Data transfers between the MCF5307 and other devices involve the following signals: Freescale Semiconductor, Inc... • • • • • Address bus (A[31:0]) Data bus (D[31:0]) Control signals (TS and TA) AS, CSx, OE, BE/BWE Attribute signals (R/W, SIZ, TT, TM, and TIP) The address bus, write data, TS, and all attribute signals change on the rising edge of BCLKO. Read data is latched into the MCF5307 on the rising edge of BCLKO.
PAGE 392
Data Transfer Operation Freescale Semiconductor, Inc. BE1 BE2 BE3 D[31:24] D[23:16] D[15:8] D[7:0] 32-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 16-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 Byte Enable Processor External Data Bus 8-Bit Port Memory BE0 Driven with indeterminate values Byte 0 Byte 1 Byte 2 Driven with indeterminate values Freescale Semiconductor, Inc... Byte 3 Figure 18-2.
PAGE 393
Freescale Semiconductor, Inc. Data Transfer Operation Table 18-3 shows the type of access as a function of match in the CSCRs and DACRs. Table 18-3. Accesses by Matches in CSCRs and DACRs Freescale Semiconductor, Inc...
PAGE 394
Data Transfer Operation Freescale Semiconductor, Inc. Next Cycle S0 S5 S1 Basic Read/Write Fast Termination S4 S2 Wait States Freescale Semiconductor, Inc... S3 Figure 18-4. Data Transfer State Transition Diagram Table 18-4 describes the states as they appear in subsequent timing diagrams. Note that the TT[1:0], TM[2:0], and TIP functions are chosen in the PAR, as described in Section 15.1.1, “Pin Assignment Register (PAR).” Table 18-4.
PAGE 395
Freescale Semiconductor, Inc. Data Transfer Operation Table 18-4. Bus Cycle States (Continued) State Freescale Semiconductor, Inc... S5 Cycle BCLKO S5 Low Description AS, CS, BE/BWE, and OE are negated on the BCLKO falling edge. The MCF5307 stops driving address lines and R/W on the rising edge of BCLKO, terminating the read or write cycle. At the same time, the MCF5307 negates TT[1:0], TM[2:0], TIP, and SIZ[1:0] on the rising edge of BCLKO.
PAGE 396
Data Transfer Operation Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 BCLKO R/W TT[1:0], TM[2:0] SIZ[1:0], A[31:0] TIP TS Freescale Semiconductor, Inc... AS, CSx BEx, OE Read D[31:0] TA Figure 18-6. Basic Read Bus Cycle Note the following characteristics of a basic read: • • • In S3, data is made available by the external device on the falling edge of BCLKO and is sampled on the rising edge of BCLKO with TA asserted.
PAGE 397
Freescale Semiconductor, Inc. Data Transfer Operation System Freescale Semiconductor, Inc... MCF5307 1. Set R/W to write 2. Place address on A[31:0] 3. Assert TT[1:0], TM[2:0], TIP, and SIZ[1:0] 4. Assert TS 5. Assert AS 6. Place data on D[31:0] 7. Negate TS 1. Sample TA low 1. Tree-state D[31:0] 2. Start next cycle 1. Decode address 2. Store data on D[31:0] 3. Assert TA 1. Negate TA Figure 18-7. Write Cycle Flowchart The write cycle timing diagram is shown in Figure 18-8.
PAGE 398
Data Transfer Operation Freescale Semiconductor, Inc. S0 S1 S4 S5 BCLKO A[31:0],TT[1:0] TM[2:0, SIZ[1:0]] R/W TIP TS AS, CSx BEx, OE Read Freescale Semiconductor, Inc... D[31:0] TA Figure 18-9. Read Cycle with Fast Termination Figure 18-10 shows a write cycle with fast termination. S0 S1 S4 S5 BCLKO A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BWEx, OE D[31:0] Write TA Figure 18-10. Write Cycle with Fast Termination 18.4.
PAGE 399
Freescale Semiconductor, Inc. Data Transfer Operation S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 BCLKO A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS Freescale Semiconductor, Inc... AS, CSx BE/BWEx OE Read D[31:0] Write TA Figure 18-11. Back-to-Back Bus Cycles Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable. 18.4.
PAGE 400
Data Transfer Operation Freescale Semiconductor, Inc. 18.4.7.1 Line Transfers A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transfers on multiple address boundaries. Table 18-5 shows allowable patterns for line accesses. Freescale Semiconductor, Inc... Table 18-5. Allowable Line Access Patterns A[3:2] Longword Accesses 00 0–4–8–C 01 4–8–C–0 10 8–C–0–4 11 C–0–4–8 18.4.7.
PAGE 401
Freescale Semiconductor, Inc. Data Transfer Operation S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 BCLKO A[31:0] TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS Freescale Semiconductor, Inc... AS, CSx BE/BWEx, OE Read D[31:0] Read Read Read TA Figure 18-13. Line Read Burst (2-1-1-1), Internal Termination Figure 18-14 shows a line access read with one wait state programmed in CSCRx to give the peripheral or memory more time to return read data.
PAGE 402
Data Transfer Operation S0 Freescale Semiconductor, Inc. S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 S6 S7 BCLKO A[3:2] = 00 A[31:0] A[3:2] = 01 R/W TT[1:0] TM[2:0] TIP SIZ[1:0] Line Longword Freescale Semiconductor, Inc... TS AS, CSx BE/BWEx, OE D[31:0] Read Read Read Read Fast Fast Fast TA Basic Figure 18-15. Line Read Burst-Inhibited, Fast, External Termination 18.4.7.
PAGE 403
Freescale Semiconductor, Inc. Data Transfer Operation Figure 18-17 shows a line burst write with one wait-state insertion. S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10S11 BCLKO A[31:0] R/W, TIP TM[2:0], TT[1:0] SIZ[1:0] TS Freescale Semiconductor, Inc... AS, CSx OE, BWE Write D[31:0] Write Write Write TA Figure 18-17. Line Write Burst (3-2-2-2) with One Wait State, Internal Termination Figure 18-18 shows a burst-inhibited line write.
PAGE 404
Misaligned Operands Freescale Semiconductor, Inc. transfer. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 BCLKO A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS Freescale Semiconductor, Inc... AS, CSx BE/BWEx, OE Read Read D[31:0] Read Read TA Figure 18-19. Longword Read from an 8-Bit Port, External Termination Note that with external termination, address signals do not change. With internal termination, Figure 18-20, A[1:0] increment for the same longword transfer.
PAGE 405
Freescale Semiconductor, Inc. Bus Errors Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address error exception. The MCF5307 converts misaligned, cache-inhibited operand accesses to multiple aligned accesses. Figure 18-21 shows the transfer of a longword operand from a byte address to a 32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1.
PAGE 406
Interrupt Exceptions Freescale Semiconductor, Inc. The MCF5307 has the following two levels of interrupt masking: • • Interrupt mask registers in the SIM compare interrupt inputs with programmable interrupt mask levels. The SIM outputs only unmasked interrupts. The status register uses a 3-bit interrupt priority mask. The core recognizes only interrupt requests of higher priority than the value in the mask. See Section 2.2.2.1, “Status Register (SR).” Freescale Semiconductor, Inc...
PAGE 407
Freescale Semiconductor, Inc. • Freescale Semiconductor, Inc... • Interrupt Exceptions The interrupt request on the interrupt control pins is raised to level 7 and stays there until an interrupt-acknowledge cycle begins. The level later drops but then returns to level 7, causing a second transition on the interrupt control lines. The interrupt request on the interrupt control pins is raised to level 7 and stays there.
PAGE 408
Freescale Semiconductor, Inc. Bus Arbitration Freescale Semiconductor, Inc... MCF5307 SYSTEM 1. Drive 0x7FFFFF on A[31:5] 2. Drive 0x0 on A[1:0] 3. Drive interrupt level on A[4:2] 4. Drive R/W to read (R/W = 1) 5. Drive SIZ[1:0] to indicate byte (SIZ[1:0] = 01) 6. Drive TT[1:0] and TM[2:0] to indicate interrupt acknowledge (TT[1:0] = 11; TM[2:0] = interrupt level) 7. Assert TS for one BCLKO cycle 1. Negate TS 2.
PAGE 409
Freescale Semiconductor, Inc. General Operation of External Master Transfers Table 18-6. MCF5307 Arbitration Protocol States (Continued) State Master Bus Explicit master MCF5307 External master External BD Description Driven Asserted The MCF5307 is explicit bus master when BG is asserted and at least one bus cycle has been initiated. It asserts BD and retains explicit mastership until BG is negated even if no active bus cycles are executed.
PAGE 410
Freescale Semiconductor, Inc. General Operation of External Master Transfers Note the following regarding external master accesses: For the MCF5307 to assert a CSx during external master accesses, CSMRn[AM] must be set. External master hits use the corresponding CSCRn settings for auto-acknowledge, byte enables, and wait states. See Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).” To enable DRAM control signals during external master accesses, DCMRn[AM] must be set.
PAGE 411
Freescale Semiconductor, Inc. General Operation of External Master Transfers NOTE: Bus timing diagrams for external master transfers are not valid for on-chip internal four-channel DMA accesses on the MCF5307. Timing diagrams describe transactions in general terms of bus cycles (Cn) rather than the states (Sn) used in the bus diagrams. Table 18-8 defines the cycles for Figure 18-24. Table 18-8. Cycles for Basic No-Wait-State External Master Access Freescale Semiconductor, Inc...
PAGE 412
Freescale Semiconductor, Inc. General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 BCLKO A[31:0] R/W TT[1:0], TM[2:0] SIZ[1:0] TIP Freescale Semiconductor, Inc... TS AS, BR 2 CS 1 BE/BWE 1 D[31:0] TA 1 BG, BD 2 HOLDREQ External Master 1 Depending on programming, these signals may or may not be driven by the 2 These signals are driven by the processor for an external master transfer. processor. Figure 18-25.
PAGE 413
Freescale Semiconductor, Inc. General Operation of External Master Transfers Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port (Continued) Cycle C6–C8 C9 Definition No-wait state data transfers 2–4 occur on the rising edges of BCLKO. TA continues to be asserted indicating completion of each transfer. TIP, CSx, and BE/BWE[3:0] are driven. TA negates on the rising edge of BCLKO along with external device’s negation of TIP.
PAGE 414
Freescale Semiconductor, Inc. General Operation of External Master Transfers shown in Figure 18-25, the MCF5307 continues to assert BD until the completion of the bus cycle. If BG is negated by the end of the bus cycle, the MCF5307 negates BD. While BG is asserted, BD remains asserted to indicate the MCF5307 is master, and it continuously drives the address bus, attributes, and control signals.
PAGE 415
Freescale Semiconductor, Inc. General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 BCLKO A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS Freescale Semiconductor, Inc... AS D[31:0] TA BG BD Implicit Mastership External Master Explicit Mastership MCF5307 Figure 18-28. Two-Wire Implicit and Explicit Bus Mastership In Figure 18-28, the external device is master during C1 and C2. It releases bus control in C3 by asserting BG to the MCF5307.
PAGE 416
Freescale Semiconductor, Inc. General Operation of External Master Transfers A1 A2 Reset A4 A3 B1 External Master D1 Implicit Master D3 Freescale Semiconductor, Inc... D2 D4 B3 B2 B4 C3 C5 Explicit Master C1 C2 C4 Figure 18-29. MCF5307 Two-Wire Bus Arbitration Protocol State Diagram Table 18-10 describes the two-wire bus arbitration protocol transition conditions. Table 18-10.
PAGE 417
Freescale Semiconductor, Inc. General Operation of External Master Transfers 1 Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from a burst-inhibited transfer are considered part of that original transfer. 2 A means asserted. 3 N means negated. 4 EM means external master. Freescale Semiconductor, Inc... 18.9.
PAGE 418
Freescale Semiconductor, Inc. General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 BCLKO A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS Freescale Semiconductor, Inc... AS D[31:0] TA BR BG BD Implicit Mastership External Master Explicit Mastership MCF5307 Figure 18-30. Three-Wire Implicit and Explicit Bus Mastership In Figure 18-30, the external device is bus master during C1 and C2, releasing control in C3, at which time the external arbiter asserts BG to the MCF5307.
PAGE 419
Freescale Semiconductor, Inc. General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 BCLKO A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS Freescale Semiconductor, Inc... AS D[31:0] TA BR BG BD External Master MCF5307 Figure 18-31. Three-Wire Bus Arbitration In Figure 18-31, the external device is bus master during C1 and C2. During C2, the MCF5307 requests the external bus because of a pending internal transfer.
PAGE 420
Freescale Semiconductor, Inc. General Operation of External Master Transfers A1 A2 Reset A4 A3 D1 B1 External Master Implicit Master D3 Freescale Semiconductor, Inc... D2 D4 B3 B2 B4 C3 C5 Explicit Master C1 C2 C4 Figure 18-32. Three-Wire Bus Arbitration Protocol State Diagram Table 18-11 lists conditions that cause state transitions. Table 18-11.
PAGE 421
Freescale Semiconductor, Inc. Reset Operation Freescale Semiconductor, Inc... Table 18-11.
PAGE 422
Reset Operation Freescale Semiconductor, Inc. 18.10.1 Master Reset Freescale Semiconductor, Inc... To perform a master reset, an external device asserts RSTI. When power is applied to the system, external circuitry should assert RSTI for a minimum of 80 CLKIN cycles after Vcc is within tolerance. Figure 18-33 is a functional timing diagram of the master reset operation, showing relationships among Vcc, RSTI, mode selects, and bus signals.
PAGE 423
Freescale Semiconductor, Inc. Reset Operation Table 18-12. Data Pin Configuration Pin D7 D[6:5] D4 Function Auto-Acknowledge Configuration (AA_CONFIG) Port Size Configuration (PS_CONFIG[1:0]) Address Configuration (ADDR_CONFIG/D4) D[3:2] Frequency of CLKIN (FREQ[1:0]) D[1:0] Ratio of BCLKO/Processor Clock {DIVIDE[1:0]) Freescale Semiconductor, Inc... See Section 17.5.5, “Data/Configuration Pins (D[7:0]).
PAGE 424
Reset Operation Freescale Semiconductor, Inc. >80 CLKIN 100K CLKIN Cycle Lock Time CLKIN 30 BCLKO BCLKO (1/2 MODE) 20 BCLKO BCLKO (1/3 MODE) Freescale Semiconductor, Inc... 15 BCLKO BCLKO (1/4 MODE) PSTCLK RSTI D[7:0] D[7:0] latched RSTO Figure 18-34. Software Watchdog Reset Timing During the software watchdog reset period, all signals that can be are driven to a high-impedance state; all those that cannot be are negated.
PAGE 425
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 19 IEEE 1149.1 Test Access Port (JTAG) This chapter describes configuration and operation of the MCF5307 JTAG test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality. 19.1 Overview The MCF5307 dedicated user-accessible test logic is fully compliant with the publication Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1.
PAGE 426
JTAG Signal Descriptions Freescale Semiconductor, Inc. Figure 19-1 is a block diagram of the MCF5307 implementation of the 1149.1 IEEE standard. The test logic includes several test data registers, an instruction register, instruction register control decode, and a 16-state dedicated TAP controller. Test Data Registers V+ TDI Boundary Scan Register M U X ID Code Freescale Semiconductor, Inc...
PAGE 427
Freescale Semiconductor, Inc. TAP Controller Freescale Semiconductor, Inc... Table 19-1. JTAG Pin Descriptions Pin Description TDI/DSI Test data input (MTMOD0 high)/development serial input (MTMOD0 low). TDI provides the serial data port for loading the JTAG boundary-scan, bypass, and instruction registers. Shifting in of data depends on the state of the JTAG controller state machine and the instruction in the instruction register. This shift occurs on the rising edge of TCK.
PAGE 428
Freescale Semiconductor, Inc. JTAG Register Descriptions 1 Test-Logic-Reset TLR <-- Value of TMS at rising edge of TCK 0 Run-Test-Idle 0 1 1 1 Select-IR-Scan SeIR Select-DR-Scan SeDR RTI 0 0 1 1 Capture-DR CaDR Capture-IR CaIR 0 Freescale Semiconductor, Inc... 0 Shift-IR Shift-DR ShDR 0 1 1 Exit1-DR Exit1-IR 1 E1DR 0 Pause-DR PaDR Pause-IR PaIR 0 0 1 1 0 Exit2-DR E2DR Exit2-IR E2IR 1 1 Update-DR UpDR 1 1 E1IR 0 0 0 ShIR 0 Update-IR UpIR 1 0 Figure 19-2.
PAGE 429
Freescale Semiconductor, Inc. JTAG Register Descriptions 19.4.1 JTAG Instruction Shift Register The MCF5307 IEEE Standard 1149.1 implementation uses a 3-bit instruction-shift register (IR) without parity. This register transfers its value to a parallel hold register and applies one of six instructions on the falling edge of TCK when the TAP state machine is in Update-IR state. To load instructions into the shift portion of the register, place the serial data on TDI before each rising edge of TCK.
PAGE 430
Freescale Semiconductor, Inc. JTAG Register Descriptions Freescale Semiconductor, Inc... Table 19-2. JTAG Instructions (Continued) Instruction Class IR Description CLAMP (CMP) Optional 110 Selects the bypass register and asserts functional reset while forcing all output and bidirectional pins configured as outputs to fixed, preloaded values in the boundary-scan update registers.
PAGE 431
Freescale Semiconductor, Inc. JTAG Register Descriptions 19.4.3 JTAG Boundary-Scan Register The MCF5307 model includes an IEEE Standard 1149.1-compliant boundary-scan register connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. This register captures signal data on the input pins, forces fixed values on the output pins, and selects the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state pins.
PAGE 432
Freescale Semiconductor, Inc. JTAG Register Descriptions Freescale Semiconductor, Inc... Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type 29 O.Pin 30 O.Pin 31 O.Pin DDATA0 O 32 O.Pin PSTCLK O 33 I.Pin CLKIN I 153 34 IO.Ctl RSTO enable — 154 35 O.Pin RSTO I/O 155 36 I.Pin RSTO I/O 156 37 O.Pin BCLKO O 157 38 I.Pin EDGESEL I 39 O.Pin TXD0 40 I.Pin RXD0 41 O.Pin RTS0 42 I.Pin CTS0 43 O.Pin TXD1 44 I.Pin 45 O.Pin 46 I.Pin CTS1 I 166 I.
PAGE 433
Freescale Semiconductor, Inc. JTAG Register Descriptions Freescale Semiconductor, Inc... Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell 65 O.Pin D8 I/O 185 O.Pin PP9 I/O 66 I.Pin D8 I/O 186 IO.Ctl PP8 enable — 67 O.Pin D9 I/O 187 I.Pin PP8 I/O 68 I.Pin D9 I/O 188 O.Pin PP8 I/O 69 O.Pin D10 I/O 189 IO.Ctl TS/R/W/SIZ enable — 70 I.Pin D10 I/O 190 IO.Ctl Address enable — 71 O.Pin D11 I/O 191 O.
PAGE 434
Freescale Semiconductor, Inc. Restrictions Freescale Semiconductor, Inc... Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type 101 O.Pin 102 I.Pin 103 104 105 Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type D26 I/O 221 O.Pin A8 I/O D26 I/O 222 I.Pin A8 I/O O.Pin D27 I/O 223 O.Pin A7 I/O I.Pin D27 I/O 224 I.Pin A7 I/O O.Pin D28 I/O 225 O.Pin A6 I/O 106 I.Pin D28 I/O 226 I.Pin A6 I/O 107 O.Pin D29 I/O 227 O.Pin A5 I/O I/O 108 I.
PAGE 435
Freescale Semiconductor, Inc. Disabling IEEE Standard 1149.1 Operation 19.6 Disabling IEEE Standard 1149.1 Operation There are two ways to use the MCF5307 without IEEE Standard 1149.1 test logic being active: Freescale Semiconductor, Inc... • Nonuse of JTAG test logic by either nontermination (disconnection) or intentionally fixing TAP logic values. The following issues must be addressed if IEEE Standard 1149.1 logic is not to be used when the MCF5307 is assembled onto a board. — IEEE Standard 1149.
PAGE 436
Freescale Semiconductor, Inc. Obtaining the IEEE Standard 1149.1 19.7 Obtaining the IEEE Standard 1149.1 The IEEE Standard 1149.1 JTAG specification is a copyrighted document and must be obtained directly from the IEEE: IEEE Standards Department 445 Hoes Lane P.O. Box 1331 Piscataway, NJ 08855-1331 USA Freescale Semiconductor, Inc... http://stdsbbs.ieee.org/ FAX: 908-981-9667 Information: 908-981-0060 or 1-800-678-4333 19-12 MCF5307 User’s Manual For More Information On This Product, Go to: www.
PAGE 437
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Chapter 20 Electrical Specifications This chapter describes the AC and DC electrical specifications and thermal characteristics for the MCF5307. Note that this information was correct at the time this book was published. As process technologies improve, there is a likelihood that this information may change. To confirm that this is the latest information, see Motorola’s ColdFire webpage, http://www.motorola.com/coldfire. 20.
PAGE 438
Freescale Semiconductor, Inc. Clock Timing Specifications voltage of Vcc = 3.3 Vdc ± 0.3 Vdc. Table 20-3. DC Electrical Specifications Freescale Semiconductor, Inc... Characteristic Symbol Min Max Units Operation voltage range Vcc 3.0 3.6 V Input high voltage VIH 2.0 3.6 V Input low voltage VIL -0.5 0.8 V Input signal undershoot — — 0.8 V Input signal overshoot — — 0.8 V Input leakage current @ 0.5/2.
PAGE 439
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications Figure 20-1 shows timings for the parameters listed in Table 20-4. C1 C3 C4 BCLKO C4 C2 C7 C8 Freescale Semiconductor, Inc... BCLKO C8 Note: Input and output AC timing specifications are measured to BCLKO with a 50-pF load capacitance (not including pin capacitance). Figure 20-1. Clock Timing Figure 20-2 shows PSTCLK timings for parameters listed in Table 20-4. C5 C6 PSTCLK C6 Figure 20-2. PSTCLK Timing 20.
PAGE 440
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications Table 20-5. Input AC Timing Specification 66 MHz Num 90 MHz Characteristic Units Min Max Min Max B5 3 BCLKO to input high impedance — 2 — 2 Bus clock B6 BCLKO to EDGESEL delay 0 7.5 0 5.5 nS 1 Inputs: BG, TA, A[23:0], PP[15:0], SIZ[1:0], R/W, TS, EDGESEL, D[31:0], IRQ[7,5,3,1], and BKPT Inputs: AS 3 Inputs: D[31:0] Freescale Semiconductor, Inc...
PAGE 441
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications Operation.” Note that Figure 20-4 does not show all signals that apply to each timing specification. See the previous tables for a complete listing. Figure 20-3 shows AC timings for normal read and write bus cycles. S0 BCLKO S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 B11 B10 A[31:0] TM[2:0] TT[1:0] SIZ[1:0] Freescale Semiconductor, Inc...
PAGE 442
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BCLKO B6 EDGESEL B15 Row A[31:0] Column TS Freescale Semiconductor, Inc... B16 SRAS B15 SCAS 1 B16 DRAMW B1 D[31:0] B16 B2 RAS B16 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL NOP =2 Figure 20-4. SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO Figure 20-5 shows an SDRAM write cycle with EDGESEL tied to buffered BCLKO.
PAGE 443
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 BCLKO B6 EDGESEL B15 Row A[31:0] Column Freescale Semiconductor, Inc... TS B16 SRAS B15 SCAS 1 B16 DRAMW B15 D[31:0] B16 RAS B16 CAS NOP ACTV 1 DACR[CASL] WRITE NOP PALL =2 Figure 20-5. SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO Figure 20-6 shows an SDRAM read cycle with EDGESEL tied high. Chapter 20.
PAGE 444
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 BCLKO B10 Row A[31:0] Column B11 TS B11a SRAS Freescale Semiconductor, Inc... B10 SCAS 1 B11a DRAMW B1 D[31:0] B11a B2 RAS B11a CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL =2 Figure 20-6. SDRAM Read Cycle with EDGESEL Tied High Figure 20-7 shows an SDRAM write cycle with EDGESEL tied high. 20-8 MCF5307 User’s Manual For More Information On This Product, Go to: www.
PAGE 445
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 BCLKO B10 Row A[31:0] Column B11 TS B11a SRAS Freescale Semiconductor, Inc... B10 SCAS1 B11a DRAMW B10 D[31:0] B11 RAS B11a B11a CAS ACTV 1 DACR[CASL] NOP WRITE NOP PALL =2 Figure 20-7. SDRAM Write Cycle with EDGESEL Tied High Figure 20-8 shows an SDRAM read cycle with EDGESEL tied low. Chapter 20. Electrical Specifications For More Information On This Product, Go to: www.
PAGE 446
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 BCLKO B13 Row A[31:0] Column TS B14 SRAS Freescale Semiconductor, Inc... B13 SCAS1 B14 DRAMW B1 D[31:0] B14 B2 RAS B14 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL =2 Figure 20-8. SDRAM Read Cycle with EDGESEL Tied Low Figure 20-9 shows an SDRAM write cycle with EDGESEL tied low. 20-10 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 447
Freescale Semiconductor, Inc. Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 BCLKO B13 Row A[31:0] Column TS B14 SRAS Freescale Semiconductor, Inc... B13 SCAS1 B14 DRAMW B13 D[31:0] B14 RAS B14 CAS ACTV 1 DACR[CASL] NOP WRITE NOP PALL =2 Figure 20-9. SDRAM Write Cycle with EDGESEL Tied Low Figure 20-10 shows AC timing showing high impedance. HIZ H1 H2 OUTPUTS Figure 20-10. AC Output Timing—High Impedance Chapter 20.
PAGE 448
Freescale Semiconductor, Inc. Reset Timing Specifications 20.4 Reset Timing Specifications Table 20-7 lists specifications for the reset timing parameters shown in Figure 20-11. Table 20-7. Reset Timing Specification 66 MHz Num Units Min Max Min Max R1 1 Valid to CLKIN (setup) 7.5 — 5.5 — nS R2 CLKIN to invalid (hold) 3 — 2 — nS R3 RSTI to invalid (hold) 3 — 2 — nS 1 Freescale Semiconductor, Inc... 90 MHz Characteristic RSTI and D[7:0] are synchronized internally.
PAGE 449
Freescale Semiconductor, Inc. Debug AC Timing Specifications Table 20-8. Debug AC Timing Specification 66 MHz Num 90 MHz Characteristic Units Min Max Min Max D4 1 DSCLK-to-DSO hold 4 4 PSTCLKs D5 DSCLK cycle time 5 5 PSTCLKs 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK. Freescale Semiconductor, Inc... Figure 20-12 shows real-time trace timing for the values in Table 20-8.
PAGE 450
Freescale Semiconductor, Inc. Timer Module AC Timing Specifications 20.6 Timer Module AC Timing Specifications Table 20-9 lists specifications for timer module AC timing parameters shown in Figure 20-14. Figure 20-14 shows timings for Table 20-9. Table 20-9. Timer Module AC Timing Specification 66 MHz Freescale Semiconductor, Inc... Num 90 MHz Characteristic Units Min Max Min Max 3 7.5 — 3 — Bus clocks — 5.
PAGE 451
Freescale Semiconductor, Inc. 2 I C Input/Output Timing Specifications 20.7 I2C Input/Output Timing Specifications Table 20-10 lists specifications for the I2C input timing parameters shown in Figure 20.8. Table 20-10. I2C Input Timing Specifications between SCL and SDA 66 MHz Num Units Min Freescale Semiconductor, Inc... 90 MHz Characteristic Max Min Max I1 Start condition hold time 2 — 2 — Bus clocks I2 Clock low period 8 — 8 — Bus clocks I3 SCL/SDA rise time (VIL = 0.
PAGE 452
Freescale Semiconductor, Inc. UART Module AC Timing Specifications Figure 20.8 shows timing for the values in Table 20-10 and Table 20-11. I2 I6 I5 SCL I1 I4 I3 I8 I9 I7 SDA Freescale Semiconductor, Inc... Figure 20-15. I2C Input/Output Timings 20.8 UART Module AC Timing Specifications Table 20-12 lists specifications for UART module AC timing parameters in Figure 20-16. Table 20-12.
PAGE 453
Freescale Semiconductor, Inc. UART Module AC Timing Specifications BCLKO U1 RXD U2 U3 Freescale Semiconductor, Inc... CTS U4 U5 TXD U6 U7 RTS U8 Figure 20-16. UART0/1 Module AC Timing—UART Mode Chapter 20. Electrical Specifications For More Information On This Product, Go to: www.freescale.
PAGE 454
Freescale Semiconductor, Inc. Parallel Port (General-Purpose I/O) Timing Specifications 20.9 Parallel Port (General-Purpose I/O) Timing Specifications Table 20-13 lists specifications for general-purpose I/O timing parameters in Figure 20-17. Table 20-13. General-Purpose I/O Port AC Timing Specifications 66 MHz Num Units Min Freescale Semiconductor, Inc... 90 MHz Characteristic Max Min P1 PP valid to BCLKO (input setup) 7.5 — 5.
PAGE 455
Freescale Semiconductor, Inc. DMA Timing Specifications 20.10 DMA Timing Specifications Table 20-14 lists specifications for DMA timing parameters shown in Figure 20-17. Table 20-14. DMA AC Timing Specifications 66 MHz Num 90 MHz Characteristic Units Min Max Min Max M1 DREQ valid to BCLKO (input setup) 7.5 — 5.5 — nS M2 BCLKO to DREQ invalid (input hold) 3 — 2 — nS Freescale Semiconductor, Inc... Figure 20-18 shows DMA AC timing. BCLKO M1 DREQ M2 Figure 20-18.
PAGE 456
Freescale Semiconductor, Inc. IEEE 1149.1 (JTAG) AC Timing Specifications 20.11 IEEE 1149.1 (JTAG) AC Timing Specifications Table 20-15 lists specifications for JTAG AC timing parameters shown in Figure 20-19. Table 20-15. IEEE 1149.1 (JTAG) AC Timing Specifications Freescale Semiconductor, Inc... Num Characteristic — TCK frequency of operation All Frequencies Max 0 10 MHz nS J1 TCK cycle time 100 — J2a TCK clock pulse high width (measured at 1.
PAGE 457
Freescale Semiconductor, Inc. IEEE 1149.1 (JTAG) AC Timing Specifications J3a J1 TCK J2b J2a J3b J4 TDI, TMS J5 J6 Freescale Semiconductor, Inc... BOUNDARY SCAN DATA INPUT J7 TRST J8 J9 TDO J10 BOUNDARY SCAN DATA OUTPUT J11 J12 Figure 20-19. IEEE 1149.1 (JTAG) AC Timing Chapter 20. Electrical Specifications For More Information On This Product, Go to: www.freescale.
PAGE 458
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... IEEE 1149.1 (JTAG) AC Timing Specifications 20-22 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 459
Freescale Semiconductor, Inc. Appendix A List of Memory Maps Freescale Semiconductor, Inc... Table A-1. SIM Registers MBAR Offset 0x000 0x004 [31:24] [23:16] [15:8] [7:0] Reset status register (RSR) [p. 6-5] System protection control register (SYPCR) [p. 6-8] Software watchdog interrupt vector register (SWIVR) [p. 6-9] Software watchdog service register (SWSR) [p. 6-9] Interrupt port assignment register (IRQPAR) [p. 9-7] Reserved Pin assignment register (PAR) [p.
PAGE 460
Freescale Semiconductor, Inc. Table A-3. Chip-Select Registers MBAR Offset 0x080 0x084 [23:16] Chip-select address register—bank 0 (CSAR0) [p. 10-6] [15:8] [7:0] Reserved1 Chip-select mask register—bank 0 (CSMR0) [p. 10-6] 0x088 Reserved1 Chip-select control register—bank 0 (CSCR0) [p. 10-8] 0x08C Chip-select address register—bank 1 (CSAR1) [p. 10-6] Reserved1 0x090 Freescale Semiconductor, Inc... [31:24] Chip-select mask register—bank 1 (CSMR1) [p.
PAGE 461
Freescale Semiconductor, Inc. Table A-3. Chip-Select Registers (Continued) MBAR Offset [31:24] [23:16] [15:8] [7:0] MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x080 Freescale Semiconductor, Inc... 0x084 Chip-select mask register—bank 0 (CSMR0) [p. 10-6] 0x088 Reserved1 Chip-select control register—bank 0 (CSCR0) [p. 10-8] 0x08C Chip-select address register—bank 1 (CSAR1) [p. 10-6] Reserved1 0x090 Chip-select mask register—bank 1 (CSMR1) [p.
PAGE 462
Freescale Semiconductor, Inc. Table A-5. General-Purpose Timer Registers MBAR Offset [23:16] [15:8] [7:0] 0x140 Timer 0 mode register (TMR0) [p. 13-3] 0x144 Timer 0 reference register (TRR0) [p. 13-4] Reserved 0x148 Timer 0 capture register (TCR0) [p. 13-4] Reserved 0x14C 0x150 Freescale Semiconductor, Inc... [31:24] Reserved Timer 0 counter (TCN0) [p. 13-5] Reserved Reserved Timer 0 event register (TER0) [p. 13-5] Reserved 0x180 Timer 1 mode register (TMR1) [p.
PAGE 463
Freescale Semiconductor, Inc. Table A-6. UART0 Module Programming Model (Continued) MBAR Offset [23:16] (Write) UART auxiliary control registers1—(UACRn) [p. 14-12] — (Read) UART interrupt status registers—(UISRn) [p. 14-13] — (Write) UART interrupt mask registers—(UIMRn) [p. 14-13] — 0x1D8 UART divider upper registers—(UDUn) [p. 14-14] — 0x1DC UART divider lower registers—(UDLn) [p. 14-14] — 0x1D4 Freescale Semiconductor, Inc...
PAGE 464
Freescale Semiconductor, Inc. Table A-7. UART1 Module Programming Model Freescale Semiconductor, Inc... MBAR Offset [31:24] [23:16] 0x200 UART mode registers1—(UMR1n) [p. 14-4], (UMR2n) [p. 14-6] — 0x204 (Read) UART status registers—(USRn) [p. 14-7] — (Write) UART clock-select register1—(UCSRn) [p. 14-8] — 0x208 0x20C 0x210 [15:8] (Read) Do not access2 — (Write) UART command registers—(UCRn) [p. 14-9] — (UART/Read) UART receiver buffers—(URBn) [p.
PAGE 465
Freescale Semiconductor, Inc. Table A-7. UART1 Module Programming Model (Continued) MBAR Offset [31:24] [23:16] 0x220– Do not access2 0x22C — 0x230 UART interrupt vector register—(UIVRn) [p. 14-15] — 0x234 (Read) UART input port registers—(UIPn) [p. 14-15] — [15:8] [7:0] Freescale Semiconductor, Inc... (Write) Do not access2 — 0x238 (Read) Do not access2 — (Write) UART output port bit set command registers—(UOP1n3) [p.
PAGE 466
Freescale Semiconductor, Inc. Table A-9. I2C Interface Memory Map MBAR Offset [31:24] [23:16] [15:8] 0x288 I2C control register (I2CR) [p. 8-8] Reserved 0x28C I2C status register (I2SR) [p. 8-9] Reserved 0x290 I2C data I/O register (I2DR) [p. 8-10] Reserved [7:0] Freescale Semiconductor, Inc... Table A-10. DMA Controller Registers MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x300 Source address register 0 (SAR0) [p. 12-6] 0x304 Destination address register 0 (DAR0) [p.
PAGE 467
Freescale Semiconductor, Inc. Table A-10. DMA Controller Registers (Continued) MBAR Offset 0x394 [31:24] [23:16] DMA interrupt vector register 2 (DIVR2) [p. 12-11] Reserved Source address register 3 (SAR3) [p. 12-6] 0x3C4 Destination address register 3 (DAR3) [p. 12-7] 0x3C8 Freescale Semiconductor, Inc... [7:0] 0x3C0 0x3CC 1 [15:8] DMA control register 3 (DCR3) [p. 12-8] Byte count register 3 (BCR24BIT = 0) 1 Reserved 0x3CC Reserved Byte count register 3 (BCR24BIT = 1) 1 (BCR3) [p.
PAGE 468
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. A-10 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 469
Freescale Semiconductor, Inc. Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Freescale Semiconductor, Inc... A Architecture. A detailed specification of requirements for a processor or computer system. It does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible implementations. Autovector.
PAGE 470
Freescale Semiconductor, Inc. its cache is supplied with data corresponding to the most recent value written to memory or to another processor’s cache. Cache flush. An operation that removes from a cache any data from a specified address range. This operation ensures that any modified data within the specified address range is written back to main memory. Cache line. The smallest unit of consecutive data or instructions that is stored in a cache. For ColdFire processors a line consists of 16 bytes.
PAGE 471
Freescale Semiconductor, Inc. Implementation. A particular processor that conforms to the ColdFire architecture, but may differ from other architecture-compliant implementations for example in design, feature set, and implementation of optional features. The ColdFire architecture has many different implementations. Imprecise mode. A memory access mode that allows write accesses to a specified memory region to occur out of order. Instruction queue.
PAGE 472
Freescale Semiconductor, Inc. N O Freescale Semiconductor, Inc... P Nop. No-operation. A single-cycle operation that does not affect registers or generate bus activity. Overflow. An condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register(s). For example, if two 16-bit numbers are multiplied, the result may not be representable in 16 bits. Pipelining.
PAGE 473
Freescale Semiconductor, Inc. System memory. The physical memory available to a processor. T Tenure. A tenure consists of three phases: arbitration, transfer, termination. There can be separate address bus tenures and data bus tenures. Throughput. The measure of the number of instructions that are processed per clock cycle. Transfer termination. The successful or unsuccessful conclusion of a data transfer. Freescale Semiconductor, Inc... U Underflow.
PAGE 474
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary-16 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 475
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
PAGE 476
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
PAGE 477
Freescale Semiconductor, Inc. INDEX PST outputs, 5-3 PULSE instruction, 5-4 signal descriptions, 19-2 TAP controller, 19-3 test logic disabling, 19-11 R Freescale Semiconductor, Inc...
PAGE 478
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
PAGE 479
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
PAGE 480
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... INDEX Index-22 MCF5307 User’s Manual For More Information On This Product, Go to: www.freescale.
PAGE 481
Freescale Semiconductor, Inc. Overview Part I: MCF5307 Processor Core Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Freescale Semiconductor, Inc...
PAGE 482
Freescale Semiconductor, Inc. 1 Part I Part I: MCF5307 Processor Core 2 ColdFire Core 3 Hardware Multiply/Accumulate (MAC) Unit 4 Local Memory 5 Debug Support Part II Freescale Semiconductor, Inc...
PAGE 483
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.
PAGE 484
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.