Datasheet

4-2 MCF5307 User’s Manual

SRAM Operation

0-modulo-32K location in the 4-Gbyte address space and conﬁgured to respond to either

instruction or data accesses.Time-critical functions can be mapped into instruction the

system stack. Other heavily-referenced data can be mapped into memory.

The following summarizes features of the MCF5307 SRAM implementation:

• 4-Kbyte SRAM, organized as 1024 x 32 bits

• Single-cycle throughput. When the pipeline is full, one access can occur per clock

cycle.

• Physical location on the processor’s high-speed local bus

• Memory location programmable on any 0-modulo-32K address boundary

• Byte, word, and longword address capabilities

• The RAM base address register (RAMBAR) deﬁnes the logical base address,

attributes, and access types for the SRAM module.

4.3 SRAM Operation

The SRAM module provides a general-purpose memory block that the ColdFire processor

can access with single-cycle throughput. The location of the memory block can be speciﬁed

to any word-aligned address in the 4-Gbyte address space by RAMBAR[BA], described in

Section 4.4.1, “SRAM Base Address Register (RAMBAR).” The memory is ideal for

storing critical code or data structures or for use as the system stack. Because the SRAM

module connects physically to the processor’s high-speed local bus, it can service

processor-initiated accesses or memory-referencing debug module commands.

Instruction fetches and data reads can be sent to both the cache and SRAM blocks

simultaneously. If the reference is mapped into a region deﬁned by the SRAM, the SRAM

provides data to the processor and any cache data is discarded. Data accessed from the

SRAM module are not cached.

Note also that the SRAM cannot be accessed by the on-chip DMAs. The on-chip system

conﬁguration allows concurrent core and DMA execution, where the core can reference

code or data from the internal SRAM or cache while performing a DMA transfer.

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