Datasheet

4-6 MCF5307 User’s Manual
Power Management
move.l 24(a7),d4 ;load byte count
asr.l #4,d4 ;divide by 16 to convert to loop count
.align 4 ;force loop on 0-mod-4 address
loop: movem.l (a0),#0xf ;read 16 bytes from source
movem.l #0xf,(a1) ;store into RAM destination
lea.l 16(a0),a0 ;increment source pointer
lea.l 16(a1),a1 ;increment destination pointer
subq.l #1,d4 ;decrement loop counter
bne.b loop ;if done, then exit, else continue
movem.l (a7),#0x1c ;restore d2/d3/d4 registers
lea.l 12(a7),a7 ;deallocate temporary space
rts
4.6 Power Management
Because processor memory references may be simultaneously sent to an SRAM module
and cache, power can be minimized by configuring RAMBAR address space masks as
precisely as possible. For example, if an SRAM is mapped to the internal instruction bus
and contains instruction data, setting the ASn mask bits associated with operand references
can decrease power dissipation. Similarly, if the SRAM contains data, setting ASn bits
associated with instruction fetches minimizes power.
Table 4-2 shows typical RAMBAR configurations.
.
4.7 Cache Overview
This section describes the MCF5307 cache implementation, including organization,
configuration, and coherency. It describes cache operations and how the cache interacts
with other memory structures.
The MCF5307 processor contains a nonblocking, 8-Kbyte, 4-way set-associative, unified
(instruction and data) cache with a 16-byte line size. The cache improves system
performance by providing low-latency access to the instruction and data pipelines. This
decouples processor performance from system memory performance, increasing bus
availability for on-chip DMA or external devices. Figure 4-2 shows the organization and
integration of the data cache.
Table 4-2. Examples of Typical RAMBAR Settings
Data Contained in SRAM RAMBAR[5–0]
Code only 0x2B
Data only 0x35
Both code and data 0x21
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