Datasheet

Chapter 4. Local Memory 4-7
Cache Organization
Figure 4-2. Unified Cache Organization
The cache supports operation of copyback, write-through, or cache-inhibited modes. The
cache lock feature can be used to guarantee deterministic response for critical code or data
areas.
A nonblocking cache services read hits or write hits from the processor while a fill (caused
by a cache allocation) is in progress. As Figure 4-2 shows, instruction and data accesses
use a single bus connected to the cache.
All addresses from the processor to the cache are physical addresses. A cache hit occurs
when an address matches a cache entry. For a read, the cache supplies data to the processor.
For a write, the processor updates the cache. If an access does not match a cache entry
(misses the cache) or if a write access must be written through to memory, the cache
performs a bus cycle on the internal bus and correspondingly on the external bus by way of
the system integration module (SIM).
The SRAM module does not implement bus snooping; cache coherency with other possible
bus masters must be maintained in software.
4.8 Cache Organization
A four-way set associative cache is organized as four ways (levels). There are 128 sets in
the 8-Kbyte cache with each line containing 16 bytes (4 longwords). Entire cache lines are
loaded from memory by burst-mode accesses that cache 4 longwords of data or
instructions. All 4 longwords must be loaded for the cache line to be valid.
Figure 4-3 shows cache organization as well as terminology used.
System
Address/
Control
Cache
Control Logic
Directory Array
Data Array
Data Path
ColdFire
Address Path
Control
Data
Address
External
Bus
Data
Control
Data
Address
Integration
Module
(SIM)
Processor
Core
Fr
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Freescale Semiconductor, Inc.
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