Datasheet

CONTENTS
Paragraph
Number
Title
Page
Number
Contents xi
Chapter 9
Interrupt Controller
9.1 Overview............................................................................................................. 9-1
9.2 Interrupt Controller Registers ............................................................................. 9-2
9.2.1 Interrupt Control Registers (ICR0–ICR9) ...................................................... 9-3
9.2.2 Autovector Register (AVR)............................................................................ 9-5
9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)................................... 9-6
9.2.4 Interrupt Port Assignment Register (IRQPAR).............................................. 9-7
Chapter 10
Chip-Select Module
10.1 Overview........................................................................................................... 10-1
10.2 Chip-Select Module Signals ............................................................................. 10-1
10.3 Chip-Select Operation....................................................................................... 10-2
10.3.1 General Chip-Select Operation..................................................................... 10-3
10.3.1.1 8-, 16-, and 32-Bit Port Sizing.................................................................. 10-4
10.3.1.2 Global Chip-Select Operation................................................................... 10-4
10.4 Chip-Select Registers........................................................................................ 10-5
10.4.1 Chip-Select Module Registers ...................................................................... 10-6
10.4.1.1 Chip-Select Address Registers (CSAR0–CSAR7)................................... 10-6
10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7)...................................... 10-6
10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7) .................................... 10-8
10.4.1.4 Code Example........................................................................................... 10-9
Chapter 11
Synchronous/Asynchronous DRAM Controller Module
11.1 Overview........................................................................................................... 11-1
11.1.1 Definitions .................................................................................................... 11-2
11.1.2 Block Diagram and Major Components....................................................... 11-2
11.2 DRAM Controller Operation............................................................................ 11-3
11.2.1 DRAM Controller Registers......................................................................... 11-3
11.3 Asynchronous Operation .................................................................................. 11-4
11.3.1 DRAM Controller Signals in Asynchronous Mode...................................... 11-4
11.3.2 Asynchronous Register Set........................................................................... 11-4
11.3.2.1 DRAM Control Register (DCR) in Asynchronous Mode ........................ 11-4
11.3.2.2 DRAM Address and Control Registers (DACR0/DACR1) ..................... 11-5
11.3.2.3 DRAM Controller Mask Registers (DMR0/DMR1) ................................ 11-7
11.3.3 General Asynchronous Operation Guidelines .............................................. 11-8
11.3.3.1 Non-Page-Mode Operation..................................................................... 11-11
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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