Datasheet

Chapter 4. Local Memory 4-21
Cache Registers
4.10 Cache Registers
This section describes the MCF5307 implementation of the Version 3 cache registers.
4.10.1 Cache Control Register (CACR)
The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the
MOVEC register instruction and can be read or written from the debug facility. A hardware
reset clears CACR, which disables the cache; however, reset does not affect the tags, state
information, or data in the cache.
Table 4-4 describes CACR fields.
31 30 29 28 27 26 25 24 23 20 19 18 17 16
Field EC — ESB DPI HLCK — CINVA —
Reset 0000_0000_0000_0000
R/W Write (R/W by debug module)
15 14 13 12 11 10 9 8 7 0
Field — DNFB DCM — DW —
Reset 0000_0000_0000_0000
R/W Write (R/W by debug module)
Rc 0x002
Figure 4-8. Cache Control Register (CACR)
Table 4-4. CACR Field Descriptions
Bits Name Description
31 EC Enable cache.
0 Cache disabled. The cache is not operational, but data and tags are preserved.
1 Cache enabled.
30 — Reserved, should be cleared.
29 ESB Enable store buffer.
0 Writes to write-through or noncachable in imprecise mode bypass the store buffer and
generate bus cycles directly. Section 4.9.5.2.1, “Push and Store Buffers,” describes the
performance penalty for this.
1 The four-entry FIFO store buffer is enabled; when imprecise mode is used, this buffer defers
pending writes to write-through or cache-inhibited regions to maximize performance.
Cache-inhibited, precise-mode accesses always bypass the store buffer.
28 DPI Disable CPUSHL invalidation.
0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified and
then invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified,
then left valid.
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