Datasheet

xii
MCF5307 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
11.3.3.2 Burst Page-Mode Operation ................................................................... 11-12
11.3.3.3 Continuous Page Mode........................................................................... 11-13
11.3.3.4 Extended Data Out (EDO) Operation..................................................... 11-15
11.3.3.5 Refresh Operation................................................................................... 11-16
11.4 Synchronous Operation................................................................................... 11-16
11.4.1 DRAM Controller Signals in Synchronous Mode...................................... 11-17
11.4.2 Using Edge Select (EDGESEL) ................................................................. 11-18
11.4.3 Synchronous Register Set........................................................................... 11-19
11.4.3.1 DRAM Control Register (DCR) in Synchronous Mode.......................... 11-19
11.4.3.2 DRAM Address and Control Registers (DACR0/DACR1)
in Synchronous Mode ......................................................................... 11-20
11.4.3.3 DRAM Controller Mask Registers (DMR0/DMR1) .............................. 11-22
11.4.4 General Synchronous Operation Guidelines............................................... 11-23
11.4.4.1 Address Multiplexing ............................................................................. 11-23
11.4.4.2 Interfacing Example................................................................................ 11-27
11.4.4.3 Burst Page Mode..................................................................................... 11-27
11.4.4.4 Continuous Page Mode........................................................................... 11-29
11.4.4.5 Auto-Refresh Operation.......................................................................... 11-31
11.4.4.6 Self-Refresh Operation ........................................................................... 11-32
11.4.5 Initialization Sequence................................................................................ 11-33
11.4.5.1 Mode Register Settings........................................................................... 11-33
11.5 SDRAM Example........................................................................................... 11-34
11.5.1 SDRAM Interface Configuration................................................................ 11-35
11.5.2 DCR Initialization....................................................................................... 11-35
11.5.3 DACR Initialization.................................................................................... 11-35
11.5.4 DMR Initialization...................................................................................... 11-37
11.5.5 Mode Register Initialization ....................................................................... 11-38
11.5.6 Initialization Code....................................................................................... 11-39
Part III
Peripheral Module
Chapter 12
DMA Controller Module
12.1 Overview........................................................................................................... 12-1
12.1.1 DMA Module Features................................................................................. 12-2
12.2 DMA Signal Description .................................................................................. 12-2
12.3 DMA Transfer Overview.................................................................................. 12-3
12.4 DMA Controller Module Programming Model................................................ 12-4
12.4.1 Source Address Registers (SAR0–SAR3).................................................... 12-6
12.4.2 Destination Address Registers (DAR0–DAR3) ........................................... 12-7
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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