Datasheet

Chapter 5. Debug Support 5-25
Background Debug Mode (BDM)
5.5.3.3.2 Write A/D Register (WAREG/WDREG)
The operand longword data is written to the specified address or data register. A write alters
all 32 register bits. A bus error response is returned if the CPU core is not halted.
Command Format:
Command Sequence
Figure 5-21. WAREG/WDREG Command Sequence
Operand Data Longword data is written into the specified address or data register.
The data is supplied most-significant word first.
Result Data Command complete status is indicated by returning 0xFFFF (with S
cleared) when the register write is complete.
1514131211109876543210
0x2 0x0 0x8 A/D Register
D[31:16]
D[15:0]
Figure 5-20. WAREG/WDREG Command Format
MS DATA
"NOT READY"
XXX
LS DATA
"NOT READY"
NEXT CMD
"NOT READY"
WDREG/WAREG
???
NEXT CMD
"CMD COMPLETE"
BERR
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...