Datasheet

5-38 MCF5307 User’s Manual
Background Debug Mode (BDM)
5.5.3.3.12 Read Debug Module Register (RDMREG)
Read the selected debug module register and return the 32-bit result. The only valid register
selection for the
RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR
clears the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered
or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.
Command/Result Formats:
Table 5-20 shows the definition of DRc encoding.
Command Sequence:
Figure 5-41. RDMREG Command Sequence
Operand Data: None
Result Data: The contents of the selected debug register are returned as a
longword value. The data is returned most-significant word first.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Command 0x2 0xD 0x4
1
1
Note 0x4 is a 3-bit field
DRc
Result D[31:16]
D[15:0]
Figure 5-40. RDMREG BDM Command/Result Formats
Table 5-20. Definition of DRc Encoding—Read
DRc[4:0] Debug Register Definition Mnemonic Initial State Page
0x00 Configuration/Status CSR 0x0 p. 5-10
0x01–0x1F Reserved ———
XXX
MS RESULT
XXX
"ILLEGAL"
NEXT CMD
LS RESULT
NEXT CMD
"NOT READY"
RDMREG
???
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