Datasheet

CONTENTS
Paragraph
Number
Title
Page
Number
Contents xvii
Chapter 18
Bus Operation
18.1 Features............................................................................................................. 18-1
18.2 Bus and Control Signals ................................................................................... 18-1
18.3 Bus Characteristics............................................................................................ 18-2
18.4 Data Transfer Operation ................................................................................... 18-3
18.4.1 Bus Cycle Execution..................................................................................... 18-4
18.4.2 Data Transfer Cycle States ........................................................................... 18-5
18.4.3 Read Cycle.................................................................................................... 18-7
18.4.4 Write Cycle................................................................................................... 18-8
18.4.5 Fast-Termination Cycles............................................................................... 18-9
18.4.6 Back-to-Back Bus Cycles........................................................................... 18-10
18.4.7 Burst Cycles................................................................................................ 18-11
18.4.7.1 Line Transfers......................................................................................... 18-12
18.4.7.2 Line Read Bus Cycles............................................................................. 18-12
18.4.7.3 Line Write Bus Cycles............................................................................ 18-14
18.4.7.4 Transfers Using Mixed Port Sizes .......................................................... 18-15
18.5 Misaligned Operands ...................................................................................... 18-16
18.6 Bus Errors ....................................................................................................... 18-17
18.7 Interrupt Exceptions........................................................................................ 18-17
18.7.1 Level 7 Interrupts........................................................................................ 18-18
18.7.2 Interrupt-Acknowledge Cycle..................................................................... 18-19
18.8 Bus Arbitration................................................................................................ 18-20
18.8.1 Bus Arbitration Signals............................................................................... 18-21
18.9 General Operation of External Master Transfers............................................ 18-21
18.9.1 Two-Device Bus Arbitration Protocol (Two-Wire Mode) ......................... 18-25
18.9.2 Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... 18-29
18.10 Reset Operation............................................................................................... 18-33
18.10.1 Master Reset ............................................................................................... 18-34
18.10.2 Software Watchdog Reset........................................................................... 18-35
Chapter 19
IEEE 1149.1 Test Access Port (JTAG)
19.1 Overview........................................................................................................... 19-1
19.2 JTAG Signal Descriptions ............................................................................... 19-2
19.3 TAP Controller.................................................................................................. 19-3
19.4 JTAG Register Descriptions ............................................................................. 19-4
19.4.1 JTAG Instruction Shift Register .................................................................. 19-5
19.4.2 IDCODE Register......................................................................................... 19-6
19.4.3 JTAG Boundary-Scan Register .................................................................... 19-7
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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