Datasheet

6-10 MCF5307 User’s Manual
Programming Model
6.2.8 PLL Clock Control for CPU STOP Instruction
The SIM contains the PLL clock control register, which is described in detail in
Section 7.2.4, “PLL Control Register (PLLCR).” PLLCR[ENBSTOP,PLLIPL] are
significant to the operation of the SIM, and are described as follows:
• PLLCR[ENBSTOP] must be set for the ColdFire CPU STOP instruction to be
acknowledged. This bit is cleared at reset and must be set for the MCF5307 to enter
low-power modes. The CPU STOP instruction stops only clocks to the core
processor. All internal modules remain clocked and can generate interrupts to restart
the ColdFire core. For example, the on-chip timer can be used to interrupt the
processor after a given timer countdown.
• PLLCR[PLLIPL] determines the minimum level at which an interrupt (decoded as
an interrupt priority level or IPL) must occur to awaken the PLL. The PLL then turns
clocks back on to the core processor and interrupt exception processing takes place.
Table 6-5 describes PLLIPL settings to be compared against the interrupt ranges that
awaken the core processor from a CPU STOP instruction.
6.2.9 Pin Assignment Register (PAR)
The pin assignment register (PAR), Figure 6-8, allows the selection of pin assignments.
Table 6-5. PLLIPL Settings
PLLIPL Description
000 Any interrupts can wake core
001 Interrupts 2–7
010 Interrupts 3–7
011 Interrupts 4–7
100 Interrupts 5–7
101 Interrupts 6–7
110 Interrupt 7 only
111 No interrupts can wake core
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 PAR6 PAR5 PAR4 PAR3 PAR2 PAR1 PAR0
PAR n = 0 PP15 PP14 PP13 PP12 PP11 PP10 PP9 PP8 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
PAR n = 1 A31 A30 A29 A28 A27 A26 A25 A24 TIP DREQ0 DREQ1 TM2 TM1 TM0 TT1 TT0
Reset Determined by driving D4/ADDR_CONFIG with a 1 or 0 when RSTI negates. The system is configured as PP[15:0] if
D4 is low; otherwise alternate pin functions selected by PAR = 1 are used.
R/W R/W
Address Address MBAR + 0x004
Figure 6-8. Pin Assignment Register (PAR)
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