Datasheet

Chapter 7. Phase-Locked Loop (PLL) 7-1
Chapter 7
Phase-Locked Loop (PLL)
This chapter describes configuration and operation of the phase-locked loop (PLL) module.
It describes in detail the registers and signals that support the PLL implementation.
7.1 Overview
The basic features of the MCF5307 PLL implementation are as follows:
• The PLL locks to the clock input (CLKIN) frequency. It provides a processor clock
(PCLK) that is twice the input clock frequency and a programmable system bus
clock output (BCLKO) that is 1/2, 1/3, or 1/4 the PCLK frequency.
• A buffered processor status clock (PSTCLK) is equal to the PCLK frequency, as
indicated in Figure 7-1. This signal is made available for system development.
The PLL module has the following three modes of operation:
• Reset mode—In reset mode, the core/bus frequency ratio and other configuration
information is sampled. At reset, the PLL asserts the reset out signal, RST
O.
• Normal mode—During normal operations, the divide ratio is programmed at reset
and is clock-multiplied to provide a maximum frequency of 90 MHz
• Reduced-power mode—In reduced-power mode, the high-speed processor core
clocks are turned off without losing the register contents so that the system can be
reenabled by an unmasked interrupt or reset.
Figure 7-1 shows the frequency relationships of PLL module clock signals.
z
Figure 7-1. PLL Module Block Diagram
PLL
CLKIN
RSTI
Divide
BCLKO
DIVIDE[1:0]
FREQ[1:0]
RSTO
PSTCLK
PCLK
CLKIN X 4 by 2
Divide by 2,
3, or 4
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eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
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