Datasheet

7-2 MCF5307 User’s Manual
PLL Operation
7.1.1 PLL:PCLK Ratios
The specifications for the clocks in the PLL module are summarized in Table 0-1.
7.2 PLL Operation
The following sections provide detailed information about the three PLL modes.
7.2.1 Reset/Initialization
The PLL receives RSTI as an input directly from the pin. Additionally, signals are
multiplexed with D[3:0]/FREQ[1:0]:DIVIDE[1:0] while RSTI
is asserted. These signals
are sampled during reset and registered by the PLL on the negation of RSTI
to provide
initialization information. FREQ[1:0] and DIVIDE[1:0] are used by the PLL to select the
CLKIN frequency range and set the CLKIN/PCLK ratio, respectively.
7.2.2 Normal Mode
PCLK is divided to create the system bus clock, BCLKO. At reset, the logic level of
DIVIDE[1:0]/D[1:0] determines the BCLKO divisor. The bus clock can be 1/2, 1/3, or 1/4
of the PCLK frequency.
7.2.3 Reduced-Power Mode
The PCLK can be turned off in a predictable manner to conserve system power. To allow
fast restart of the MCF5307 processor core, the PLL continues to operate at the frequency
configured at reset. PCLK is disabled using the CPU STOP instruction and resumes normal
operation on interrupt, as described in Section 7.2.4, “PLL Control Register (PLLCR).”
Table 0-1. PLL Clock Specifications
Symbol Description Frequency
— PLL lock time 2.2 mS with CLKIN running at 45 MHz
CLKIN Input clock 16.67 MHz–45 MHz
PCLK Internal processor clock 33.34 MHz
–90 MHz (CLKIN x 2)
PSTCLK Processor status clock 33.34 MHz
–90 MHz (CLKIN x 2)
BCLKO Output clock 16.67 MHz
–45 MHz 11.11 MHz–30 MHz 8.24 MHz–22.5 MHz
BCLKO/PCLK ratio 1/2 1/3 1/4
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eescale S
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