Datasheet

8-2 MCF5307 User’s Manual
Interface Features
• Acknowledge bit generation/detection
• Bus-busy detection
Figure 8-1 is a block diagram of the I
2
C module.
Figure 8-1. I
2
C Module Block Diagram
Figure 8-1 shows the relationships of the I
2
C registers, listed below:
•I
2
C address register (IADR)
•I
2
C frequency divider register (IFDR)
•I
2
C control register (I2CR)
•I
2
C status register (I2SR)
•I
2
C data I/O register (I2DR)
These registers are described in Section 8.5, “Programming Model.”
Address
Compare
In/Out
Data
Shift
Start, Stop,
Input
Sync
Clock
Control
Registers and ColdFire Interface
Address Decode
I
2
C Address
Data MUX
SDASCL
AddressIRQ Data
and
Arbitration
Control
Register
Internal Bus
Register
(IADR)
I
2
C Frequency
Divider Register
(IFDR)
I
2
C Data
I/O Register
(I2DR)
I
2
C Status
Register
(I2SR)
I
2
C Control
Register
(I2CR)
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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