Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
Illustrations xxi
6-9 Default Bus Master Register (MPARK)..................................................................... 6-11
6-10 Round Robin Arbitration (PARK = 00)...................................................................... 6-12
6-11 Park on Master Core Priority (PARK = 01) ............................................................... 6-13
6-12 Park on DMA Module Priority (PARK = 10)............................................................. 6-13
6-13 Park on Current Master Priority (PARK = 01)........................................................... 6-14
7-1 PLL Module Block Diagram ........................................................................................7-1
7-2 PLL Control Register (PLLCR).................................................................................... 7-3
7-3 CLKIN, PCLK, PSTCLK, and BCLKO Timing.......................................................... 7-5
7-4 Reset and Initialization Timing..................................................................................... 7-6
7-5 PLL Power Supply Filter Circuit.................................................................................. 7-6
8-1 I
2
C Module Block Diagram.......................................................................................... 8-2
8-2 I
2
C Standard Communication Protocol ........................................................................ 8-3
8-3 Repeated START.......................................................................................................... 8-4
8-4 Synchronized Clock SCL.............................................................................................. 8-5
8-5 I
2
C Address Register (IADR).......................................................................................8-6
8-6 I
2
C Frequency Divider Register (IFDR)....................................................................... 8-7
8-7 I
2
C Control Register (I2CR).........................................................................................8-8
8-8 I
2
CR Status Register (I2SR) ......................................................................................... 8-9
8-9 I
2
C Data I/O Register (I2DR) ..................................................................................... 8-10
8-10 Flow-Chart of Typical I
2
C Interrupt Routine ............................................................. 8-14
9-1 Interrupt Controller Block Diagram.............................................................................. 9-1
9-2 Interrupt Control Registers (ICR0–ICR9) ....................................................................9-3
9-3 Autovector Register (AVR).......................................................................................... 9-5
9-4 Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR)......................... 9-7
9-5 Interrupt Port Assignment Register (IRQPAR)............................................................ 9-7
10-1 Connections for External Memory Port Sizes ............................................................10-4
10-2 Chip Select Address Registers (CSAR0–CSAR7) ..................................................... 10-6
10-3 Chip Select Mask Registers (CSMRn) ....................................................................... 10-7
10-4 Chip-Select Control Registers (CSCR0–CSCR7) ...................................................... 10-8
11-1 Asynchronous/Synchronous DRAM Controller Block Diagram ...............................11-2
11-2 DRAM Control Register (DCR) (Asynchronous Mode)............................................ 11-5
11-3 DRAM Address and Control Registers (DACR0/DACR1)........................................ 11-6
11-4 DRAM Controller Mask Registers (DMR0 and DMR1)............................................ 11-7
11-5 Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4) .......................... 11-11
11-6 Basic Non-Page-Mode Operation RCD = 1, RNCN = 0 (5-5-5-5) .......................... 11-12
11-7 Burst Page-Mode Read Operation (4-3-3-3)............................................................. 11-13
11-8 Burst Page-Mode Write Operation (4-3-3-3)............................................................ 11-13
11-9 Continuous Page-Mode Operation............................................................................ 11-14
11-10 Write Hit in Continuous Page Mode......................................................................... 11-15
11-11 EDO Read Operation (3-2-2-2) ................................................................................11-15
11-12 DRAM Access Delayed by Refresh .........................................................................11-16
11-13 MCF5307 SDRAM Interface.................................................................................... 11-18
11-14 Using EDGESEL to Change Signal Timing............................................................. 11-19
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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