Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
xxii MCF5307 User’s Manual
11-15 DRAM Control Register (DCR) (Synchronous Mode) ............................................ 11-19
11-16 DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20
11-17 DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22
11-18 Burst Read SDRAM Access..................................................................................... 11-28
11-19 Burst Write SDRAM Access .................................................................................... 11-29
11-20 Synchronous, Continuous Page-Mode Access—Consecutive Reads....................... 11-30
11-21 Synchronous, Continuous Page-Mode Access—Read after Write........................... 11-31
11-22 Auto-Refresh Operation............................................................................................ 11-32
11-23 Self-Refresh Operation ............................................................................................. 11-32
11-24 Mode Register Set (mrs) Command .........................................................................11-34
11-25 Initialization Values for DCR................................................................................... 11-35
11-26 SDRAM Configuration............................................................................................. 11-36
11-27 DACR Register Configuration.................................................................................. 11-36
11-28 DMR0 Register......................................................................................................... 11-37
11-29 Mode Register Mapping to MCF5307 A[31:0] ........................................................ 11-38
12-1 DMA Signal Diagram................................................................................................. 12-1
12-2 Dual-Address Transfer................................................................................................ 12-3
12-3 Single-Address Transfers............................................................................................ 12-4
12-4 Source Address Registers (SARn).............................................................................. 12-6
12-5 Destination Address Registers (DARn)...................................................................... 12-7
12-6 Byte Count Registers (BCRn)—BCR24BIT = 1........................................................ 12-7
12-7 BCRn—BCR24BIT = 0.............................................................................................. 12-8
12-8 DMA Control Registers (DCRn) ............................................................................... 12-8
12-9 DMA Status Registers (DSRn)................................................................................ 12-10
12-10 DMA Interrupt Vector Registers (DIVRn)............................................................... 12-11
12-11 DREQ Timing Constraints, Dual-Address DMA Transfer....................................... 12-15
12-12 Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer................... 12-16
12-13 Single-Address DMA Transfer................................................................................. 12-17
13-1 Timer Block Diagram ................................................................................................. 13-1
13-2 Timer Mode Registers (TMR0/TMR1) ......................................................................13-3
13-3 Timer Reference Registers (TRR0/TRR1) ................................................................. 13-4
13-4 Timer Capture Register (TCR0/TCR1) ......................................................................13-5
13-5 Timer Counters (TCN0/TCN1)................................................................................... 13-5
13-6 Timer Event Registers (TER0/TER1)......................................................................... 13-5
14-1 Simplified Block Diagram.......................................................................................... 14-1
14-2 UART Mode Registers 1 (UMR1n)............................................................................ 14-5
14-3 UART Mode Register 2 (UMR2n) ............................................................................. 14-6
14-4 UART Status Register (USRn)................................................................................... 14-7
14-5 UART Clock-Select Register (UCSRn)...................................................................... 14-8
14-6 UART Command Register (UCRn)............................................................................ 14-9
14-7 UART Receiver Buffer (URB0)............................................................................... 14-11
14-8 UART Transmitter Buffer (UTB0)........................................................................... 14-12
14-9 UART Input Port Change Register (UIPCRn).......................................................... 14-12
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eescale S
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Freescale Semiconductor, Inc.
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