Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
Illustrations xxiii
14-10 UART Auxiliary Control Register (UACRn)........................................................... 14-13
14-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-13
14-12 UART Divider Upper Register (UDUn)................................................................... 14-14
14-13 UART Divider Lower Register (UDLn)................................................................... 14-14
14-14 UART Interrupt Vector Register (UIVRn)............................................................... 14-15
14-15 UART Input Port Register (UIPn)............................................................................ 14-15
14-17 UART Block Diagram Showing External and Internal Interface Signals................ 14-16
14-16 UART Output Port Command Register (UOP1/UOP0)........................................... 14-16
14-18 UART/RS-232 Interface........................................................................................... 14-17
14-19 Clocking Source Diagram......................................................................................... 14-18
14-20 Transmitter and Receiver Functional Diagram......................................................... 14-20
14-21 Transmitter Timing Diagram.................................................................................... 14-22
14-22 Receiver Timing........................................................................................................ 14-23
14-23 Automatic Echo ........................................................................................................14-25
14-24 Local Loop-Back ......................................................................................................14-26
14-25 Remote Loop-Back................................................................................................... 14-26
14-26 Multidrop Mode Timing Diagram ............................................................................ 14-27
14-27 UART Mode Programming Flowchart..................................................................... 14-30
15-1 Parallel Port Pin Assignment Register (PAR) ............................................................ 15-1
15-2 Port A Data Direction Register (PADDR).................................................................. 15-2
15-3 Port A Data Register (PADAT).................................................................................. 15-3
16-1 Mechanical Diagram................................................................................................... 16-9
16-2 MCF5307 Case Drawing (General View) ................................................................ 16-10
16-3 Case Drawing (Details)............................................................................................. 16-11
17-1 MCF5307 Block Diagram with Signal Interfaces ......................................................17-2
18-1 Signal Relationship to BCLKO for Non-DRAM Access ........................................... 18-2
18-2 Connections for External Memory Port Sizes ............................................................18-4
18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4
18-4 Data Transfer State Transition Diagram..................................................................... 18-6
18-5 Read Cycle Flowchart................................................................................................. 18-7
18-6 Basic Read Bus Cycle................................................................................................. 18-8
18-7 Write Cycle Flowchart................................................................................................ 18-9
18-8 Basic Write Bus Cycle................................................................................................ 18-9
18-9 Read Cycle with Fast Termination ...........................................................................18-10
18-10 Write Cycle with Fast Termination........................................................................... 18-10
18-11 Back-to-Back Bus Cycles ......................................................................................... 18-11
18-12 Line Read Burst (2-1-1-1), External Termination .................................................... 18-12
18-13 Line Read Burst (2-1-1-1), Internal Termination .....................................................18-13
18-14 Line Read Burst (3-2-2-2), External Termination .................................................... 18-13
18-15 Line Read Burst-Inhibited, Fast, External Termination............................................ 18-14
18-16 Line Write Burst (2-1-1-1), Internal/External Termination...................................... 18-14
18-17 Line Write Burst (3-2-2-2) with One Wait State, Internal Termination................... 18-15
18-18 Line Write Burst-Inhibited, Internal Termination ....................................................18-15
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...