Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
xxiv MCF5307 User’s Manual
18-19 Longword Read from an 8-Bit Port, External Termination...................................... 18-16
18-20 Longword Read from an 8-Bit Port, Internal Termination....................................... 18-16
18-21 Example of a Misaligned Longword Transfer (32-Bit Port) ....................................18-17
18-22 Example of a Misaligned Word Transfer (32-Bit Port)............................................ 18-17
18-23 Interrupt-Acknowledge Cycle Flowchart .................................................................18-20
18-24 Basic No-Wait-State External Master Access .......................................................... 18-22
18-25 External Master Burst Line Access to 32-Bit Port.................................................... 18-24
18-26 MCF5307 Two-Wire Mode Bus Arbitration Interface............................................. 18-25
18-27 Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26
18-28 Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27
18-29 MCF5307 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28
18-30 Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30
18-31 Three-Wire Bus Arbitration...................................................................................... 18-31
18-32 Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32
18-33 Master Reset Timing................................................................................................. 18-34
18-34 Software Watchdog Reset Timing............................................................................ 18-36
19-1 JTAG Test Logic Block Diagram............................................................................... 19-2
19-2 JTAG TAP Controller State Machine......................................................................... 19-4
19-4 Disabling JTAG in JTAG Mode............................................................................... 19-11
19-5 Disabling JTAG in Debug Mode.............................................................................. 19-11
20-1 Clock Timing .............................................................................................................. 20-3
20-2 PSTCLK Timing......................................................................................................... 20-3
20-3 AC Timings—Normal Read and Write Bus Cycles ................................................... 20-5
20-4 SDRAM Read Cycle with EDGESEL Tied to Buffered BCLKO.............................. 20-6
20-5 SDRAM Write Cycle with EDGESEL Tied to Buffered BCLKO............................. 20-7
20-6 SDRAM Read Cycle with EDGESEL Tied High....................................................... 20-8
20-7 SDRAM Write Cycle with EDGESEL Tied High...................................................... 20-9
20-8 SDRAM Read Cycle with EDGESEL Tied Low ..................................................... 20-10
20-9 SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-11
20-10 AC Output Timing—High Impedance...................................................................... 20-11
20-11 Reset Timing............................................................................................................. 20-12
20-12 Real-Time Trace AC Timing.................................................................................... 20-13
20-13 BDM Serial Port AC Timing.................................................................................... 20-13
20-14 Timer Module AC Timing........................................................................................ 20-14
20-15 I
2
C Input/Output Timings......................................................................................... 20-16
20-16 UART0/1 Module AC Timing—UART Mode......................................................... 20-17
20-17 General-Purpose I/O Timing..................................................................................... 20-18
20-18 DMA Timing ............................................................................................................ 20-19
20-19 IEEE 1149.1 (JTAG) AC Timing............................................................................. 20-21
Fr
eescale S
emiconduct
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, I
Freescale Semiconductor, Inc.
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