Datasheet

Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-21
Synchronous Operation
Table 11-13 describes DACRn fields.
Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode)
Bit Name Description
31–18 BA Base address register. With DCMR[BAM], determines the address range in which the associated
DRAM block is located. Each BA bit is compared with the corresponding address of the current bus
cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the
same as in asynchronous operation.
17–16 — Reserved, should be cleared.
15 RE Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM
block.
0 Do not refresh associated DRAM block
1 Refresh associated DRAM block
14 — Reserved, should be cleared.
13–12 CASL CAS
latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with
manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature:
Parameter
Number of Bus Clocks
CASL= 00 CASL = 01 CASL= 10 CASL= 11
t
RCD
—SRAS assertion to SCAS assertion 1 2 3 3
t
CASL
—SCAS assertion to data out 1 2 3 3
t
RAS
—ACTV command to precharge command 2 4 6 6
t
RP
—Precharge command to ACTV command 1 2 3 3
t
RWL,
t
RDL
—Last data input to precharge
command
1111
t
EP
—Last data out to precharge command) 1 1 1 1
11 — Reserved, should be cleared.
10–8 CBM Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and
bank select lines to correspond to different addresses, these resources are programmable. CBM
determines the addresses onto which these functions are multiplexed.
CBM Command Bit Bank Select Bits
000 17 18 and up
001 18 19 and up
010 19 20 and up
011 20 21 and up
100 21 22 and up
101 22 23 and up
110 23 24 and up
111 24 25 and up
This encoding and the address multiplexing scheme handle common SDRAM organizations. Bank
select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits.
7 — Reserved, should be cleared.
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eescale S
emiconduct
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