Datasheet

xxviii MCF5307 User’s Manual
TABLES
Table
Number
Title
Page
Number
11-34 DCR Initialization Values......................................................................................... 11-35
11-35 DACR Initialization Values...................................................................................... 11-36
11-36 DMR0 Initialization Values...................................................................................... 11-37
11-37 Mode Register Initialization .....................................................................................11-38
12-1 DMA Signals .............................................................................................................. 12-2
12-2 Memory Map for DMA Controller Module Registers................................................ 12-5
12-3 DCRn Field Descriptions............................................................................................ 12-8
12-4 DSRn Field Descriptions .......................................................................................... 12-10
13-1 General-Purpose Timer Module Memory Map .......................................................... 13-3
13-2 TMRn Field Descriptions ........................................................................................... 13-4
13-3 TERn Field Descriptions............................................................................................. 13-6
13-5 Calculated Time-out Values (90-MHz Processor Clock)........................................... 13-7
14-1 UART Module Programming Model.......................................................................... 14-3
14-2 UMR1n Field Descriptions......................................................................................... 14-5
14-3 UMR2n Field Descriptions......................................................................................... 14-6
14-4 USRn Field Descriptions ............................................................................................ 14-7
14-5 UCSRn Field Descriptions.......................................................................................... 14-9
14-6 UCRn Field Descriptions............................................................................................ 14-9
14-7 UIPCRn Field Descriptions ...................................................................................... 14-12
14-8 UACRn Field Descriptions....................................................................................... 14-13
14-9 UISRn/UIMRn Field Descriptions ........................................................................... 14-14
14-10 UIVRn Field Descriptions ........................................................................................ 14-15
14-11 UIPn Field Descriptions............................................................................................ 14-15
14-12 UOP1/UOP0 Field Descriptions............................................................................... 14-16
14-13 UART Module Signals ............................................................................................. 14-17
14-14 UART Module Initialization Sequence ....................................................................14-29
15-1 Parallel Port Pin Descriptions..................................................................................... 15-2
15-2 PADDR Field Description.......................................................................................... 15-2
15-3 Relationship between PADAT Register and Parallel Port Pin (PP) ........................... 15-3
16-1 Pins 1–52 (Left, Top-to-Bottom)................................................................................ 16-1
16-2 Pins 53–104 (Bottom, Left-to-Right).......................................................................... 16-3
16-3 Pins 105–156 (Right, Bottom-to-Top)........................................................................ 16-4
16-4 Pins 157–208 (Top, Right-to-Left) ............................................................................. 16-6
16-5 Dimensions ............................................................................................................... 16-11
17-1 MCF5307 Signal Index............................................................................................... 17-3
17-2 Data Pin Configuration ............................................................................................... 17-6
17-3 Bus Cycle Size Encoding............................................................................................ 17-7
17-4 Bus Cycle Transfer Type Encoding............................................................................ 17-9
17-5 TM[2:0] Encodings for TT = 00 (Normal Access)..................................................... 17-9
17-6 TM0 Encoding for DMA as Master (TT = 01)........................................................... 17-9
17-7 TM[2:1] Encoding for DMA as Master (TT = 01) ................................................... 17-10
17-8 TM[2:0] Encodings for TT = 10 (Emulator Access) ................................................ 17-10
17-9 TM[2:0] Encodings for TT = 11 (Interrupt Level) ................................................... 17-10
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eescale S
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