Datasheet

12-8 MCF5307 User’s Manual
DMA Controller Module Programming Model
Figure 12-7. BCRn—BCR24BIT = 0
DSR[DONE], shown in Figure 12-9, is set when the block transfer is complete.
When a transfer sequence is initiated and BCRn[BCR] is not divisible by 16, 4, or 2 when
the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set
and no transfer occurs. See Section 12.4.5, “DMA Status Registers (DSR0–DSR3).”
12.4.4 DMA Control Registers (DCR0–DCR3)
DCRn, Figure 12-8, is used for configuring the DMA controller module. Note that
DCR[AT] is available only if BCR24BIT = 1.
Table 12-3 describes DCR fields.
Bit
151413 1211109876543210
Field BCR
Reset 0000_0000_0000_0000
R/W
Addr MBAR + 0x30C, 0x34C, 0x38C, 0x3AC
31 30 29 28 27 25 24 23 22 21 20 19 18 17 16
Field INT EEXT CS AA BWC SAA S_RW SINC SSIZE DINC DSIZE START
Reset 0000_0000_0000_0000
R/W R/W
15 14 0
Field AT
1
1
Available only if BCR24BIT = 1, otherwise reserved.
—
Reset 0
N/A
R/W R/W
Address MBAR + 0x308, 0x348, 0x388, 0x3A8
Figure 12-8. DMA Control Registers (DCRn)
Table 12-3. DCRn Field Descriptions
Bits Name Description
31 INT Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a
transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
30 EEXT Enable external request. Care should be taken because a collision can occur between the START
bit and DREQ
when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. Internal request is always enabled. It is initiated by
writing a 1 to the START bit.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...