Datasheet

12-18 MCF5307 User’s Manual
DMA Controller Module Functional Description
4. Repeat longwords until SAR = 0x00F0.
5. Read byte from 0x00F0—write byte, increment SAR.
If DSIZE is another size, data writes are optimized to write the largest size allowed based
on the address, but not exceeding the configured size.
12.5.4.3 Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to
another device. DCR[BWC] provides seven levels of block transfer sizes. If the BCR
decrements to a multiple of the decode of the BWC, the DMA bus request negates until the
bus cycle terminates. If a request is pending, the arbiter may then pass bus mastership to
another device. If auto-alignment is enabled, DCR[AA] = 1, the BCR may skip over the
programmed boundary, in which case, the DMA bus request is not negated.
If BWC = 000, the request signal remains asserted until BCR reaches zero. DMA has
priority over the core. Note that in this scheme, the arbiter can always force the DMA to
relinquish the bus. See Section 6.2.10.1, “Default Bus Master Park Register (MPARK).”
12.5.5 Termination
An unsuccessful transfer can terminate for one of the following reasons:
• Error conditions—When the MCF5307 encounters a read or write cycle that
terminates with an error condition, DSR[BES] is set for a read and DSR[BED] is set
for a write before the transfer is halted. If the error occurred in a write cycle, data in
the internal holding register is lost.
• Interrupts—If DCR[INT] is set, the DMA drives the appropriate internal interrupt
signal. The processor can read DSR to determine whether the transfer terminated
successfully or with an error. DSR[DONE] is then written with a one to clear the
interrupt and the DONE and error bits.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...